diff options
| author | Zhao Qiang <B45475@freescale.com> | 2013-09-04 02:11:27 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 23:13:11 (GMT) |
| commit | ffee1dde3c4cb2721c56c78e0360affec1c23d3f (patch) | |
| tree | fc87c859def7c217c5caca59a4a9ac3f0eae69bc /board/freescale/corenet_ds/eth_hydra.c | |
| parent | d56898249c09f8264fc398dd209c293116a293c9 (diff) | |
| download | u-boot-ffee1dde3c4cb2721c56c78e0360affec1c23d3f.tar.xz | |
SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.
QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.
However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Diffstat (limited to 'board/freescale/corenet_ds/eth_hydra.c')
| -rw-r--r-- | board/freescale/corenet_ds/eth_hydra.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a594efc..35825c4 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -76,6 +76,8 @@ #define BRDCFG2_REG_GPIO_SEL 0x20 +#define PHY_BASE_ADDR 0x00 + /* * BRDCFG1 mask and value for each MAC * @@ -365,6 +367,7 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; + struct mii_dev *bus; printf("Initializing Fman\n"); @@ -470,6 +473,9 @@ int board_eth_init(bd_t *bis) } } + bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); + set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); + /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the |