diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 18:37:48 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 19:41:39 (GMT) |
| commit | c63e137014cf148bc1d234128941dccee3d519ae (patch) | |
| tree | afb69c22c33459d14a174973083e2a70e5f49ea7 /board/freescale/corenet_ds | |
| parent | b61e06156660579ea6e248abd2506ebdd85e7a14 (diff) | |
| download | u-boot-c63e137014cf148bc1d234128941dccee3d519ae.tar.xz | |
powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/corenet_ds')
| -rw-r--r-- | board/freescale/corenet_ds/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index da284cd..517e87f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -56,14 +56,14 @@ phys_size_t fixed_sdram(void) ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #if (CONFIG_NUM_DDR_CONTROLLERS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); #endif /* |