diff options
| author | Wang Huan <b18965@freescale.com> | 2014-09-05 05:52:44 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 17:30:34 (GMT) |
| commit | 550e3dc090888fbc9c0fc4066541a2b4eb88c47b (patch) | |
| tree | 3d82f1a3c9c30a85c612e487a73df2cc767173d7 /board/freescale/ls1021aqds/ls1021aqds_qixis.h | |
| parent | ef87cab66492fe530bb6ec2e499b030c5ae60286 (diff) | |
| download | u-boot-550e3dc090888fbc9c0fc4066541a2b4eb88c47b.tar.xz | |
arm: ls102xa: Add basic support for LS1021AQDS board
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'board/freescale/ls1021aqds/ls1021aqds_qixis.h')
| -rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h new file mode 100644 index 0000000..09b3be2 --- /dev/null +++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1021AQDS_QIXIS_H__ +#define __LS1021AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1021AQDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define QIXIS_SRDS1CLK_100 0x0 + +#endif |