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| author | Qianyu Gong <qianyu.gong@nxp.com> | 2016-04-25 08:38:35 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-18 15:51:44 (GMT) |
| commit | 869bf86811a7c942dc48b294d5c0442b1f57ab53 (patch) | |
| tree | bc8b01eeab4b8d0260e9559efb3775c8a4b3e60e /board/freescale/ls1043ardb/cpld.h | |
| parent | 12cbf20d78f93c86e287d86ff863926e5cde9355 (diff) | |
| download | u-boot-869bf86811a7c942dc48b294d5c0442b1f57ab53.tar.xz | |
armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1043ardb/cpld.h')
| -rw-r--r-- | board/freescale/ls1043ardb/cpld.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif |