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| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2017-11-30 06:30:54 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-18 05:29:08 (GMT) |
| commit | 55540f32f937416ae2e1879663d354a264939584 (patch) | |
| tree | 8d78860187c3ed9d0b7a30d5cd65d8a93fcff47a /board/freescale/ls1088a/ddr.c | |
| parent | 2586b3ab5805d1a13c24660500f2a9fe63e3d786 (diff) | |
| download | u-boot-55540f32f937416ae2e1879663d354a264939584.tar.xz | |
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Diffstat (limited to 'board/freescale/ls1088a/ddr.c')
0 files changed, 0 insertions, 0 deletions