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| author | York Sun <yorksun@freescale.com> | 2015-11-04 18:03:22 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-14 02:27:28 (GMT) |
| commit | c4243ac9e2713897a63dcdc3a96bf088fdb49866 (patch) | |
| tree | ff5766eef6dc2f238791a238bccbc484941373cc /board/freescale/ls2080ardb/ddr.c | |
| parent | 6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3 (diff) | |
| download | u-boot-c4243ac9e2713897a63dcdc3a96bf088fdb49866.tar.xz | |
armv8/ls2080aqds: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls2080ardb/ddr.c')
0 files changed, 0 insertions, 0 deletions