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authorPriyanka Jain <priyanka.jain@nxp.com>2017-04-25 04:42:31 (GMT)
committerYork Sun <york.sun@nxp.com>2017-05-23 16:12:26 (GMT)
commit5193405a163aa9bab068680167fdeb0e1008e7b5 (patch)
treee7b6504ffc29fca66ddb342d2ba11229f04bd85e /board/freescale/ls2080ardb/ls2080ardb.c
parent3098e539d6a67df9f2a3c402d62147fa10422150 (diff)
downloadu-boot-5193405a163aa9bab068680167fdeb0e1008e7b5.tar.xz
board: freescale: ls2080ardb: Enable SD interface for RevF board
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls2080ardb/ls2080ardb.c')
-rw-r--r--board/freescale/ls2080ardb/ls2080ardb.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index ea05ec6..c2aa101 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (C) 2017 NXP Semiconductors
* Copyright 2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
@@ -205,6 +206,23 @@ int board_early_init_f(void)
int misc_init_r(void)
{
+#ifdef CONFIG_FSL_QIXIS
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ /*
+ * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
+ * which needs to be programmed to enable high speed SD interface
+ * by setting GPIO4_10 output to zero
+ */
+ if ((sw & 0xf) == 0x5) {
+ out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
+ in_le32(GPIO4_GPDIR_ADDR)));
+ out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
+ in_le32(GPIO4_GPDAT_ADDR)));
+ }
+#endif
+
if (hwconfig("sdhc"))
config_board_mux(MUX_TYPE_SDHC);