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| author | Shaohui Xie <Shaohui.Xie@nxp.com> | 2016-01-28 07:38:15 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-03-21 19:42:10 (GMT) |
| commit | abc7d0f75c078524f713cb2d4b4efe1b1a122c60 (patch) | |
| tree | 93b1b221776309ecda58810f5ba0e2093ecc51f6 /board/freescale/ls2080ardb | |
| parent | 2b690b9837b4bb6d3598e4259581e399d078bff8 (diff) | |
| download | u-boot-abc7d0f75c078524f713cb2d4b4efe1b1a122c60.tar.xz | |
armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls2080ardb')
| -rw-r--r-- | board/freescale/ls2080ardb/ls2080ardb.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..12638df 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -149,6 +149,7 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; u32 val; init_final_memctl_regs(); @@ -170,6 +171,9 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); + /* invert AQR405 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + return 0; } |