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| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2014-11-06 02:51:59 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 17:36:13 (GMT) |
| commit | afff13790e38eea6378801616b1749464f796ad3 (patch) | |
| tree | 2539f31c93c06018f636514d8121c80a2470ab02 /board/freescale/mpc837xerdb | |
| parent | da419027afe8336284f5db9867a880dfb3b3ab26 (diff) | |
| download | u-boot-afff13790e38eea6378801616b1749464f796ad3.tar.xz | |
ls1021aqds: set the default I2C channel before DDR init
When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/mpc837xerdb')
0 files changed, 0 insertions, 0 deletions