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authorDave Liu <daveliu@freescale.com>2008-10-28 09:53:38 (GMT)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-04 04:44:48 (GMT)
commit9b0ad1b1c7a15ff674978705c7c52264978dc5d8 (patch)
tree5f36c4042cbf9b782a025e446c56d2db8f182db4 /board/freescale/mpc8536ds/mpc8536ds.c
parent2077e348c2a84901022ad95311b47b70361e6daa (diff)
downloadu-boot-9b0ad1b1c7a15ff674978705c7c52264978dc5d8.tar.xz
85xx: remove the unused ddr_enable_ecc in the board file
The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8536ds/mpc8536ds.c')
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 6fed4ea..2538483 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -41,10 +41,6 @@
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
phys_size_t fixed_sdram(void);
int checkboard (void)
@@ -73,12 +69,6 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
puts(" DDR: ");
return dram_size;
}