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| author | Abbas Raza <Abbas_Raza@mentor.com> | 2013-03-25 09:13:34 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-04-03 09:26:28 (GMT) |
| commit | aad4659a2fde4b69e8124d6fe8b57bf28d3c747d (patch) | |
| tree | 93aa84da33f8f22c00314063e133af6b9675e1e2 /board/freescale/mx6qsabrelite | |
| parent | 2feae93ac0cba77cda1a4e0e4af8bd73135f5371 (diff) | |
| download | u-boot-aad4659a2fde4b69e8124d6fe8b57bf28d3c747d.tar.xz | |
mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board
Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.
It is tested with a MMCplus card.
Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Diffstat (limited to 'board/freescale/mx6qsabrelite')
| -rw-r--r-- | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 5b69a6d..0e25613 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].max_bus_width = 4; + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: |