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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2013-09-13 06:46:02 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 23:15:17 (GMT) |
| commit | ad89da0c33f8d9f5a4e28974ad594ff679a74e8c (patch) | |
| tree | 532209db1eed47a8e509578e312175c97b0a92d9 /board/freescale/p1010rdb/tlb.c | |
| parent | 5536aeb09b672e2541663fdc9370e2bc174dbae9 (diff) | |
| download | u-boot-ad89da0c33f8d9f5a4e28974ad594ff679a74e8c.tar.xz | |
board/p1010rdb: add pin mux and sdhc support in any boot
Since pins multiplexing, SDHC shares signals with IFC, with this patch:
To enable SDHC in case of NOR/NAND/SPI boot
a) For temporary use case in runtime without reboot system
run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
b) For long-term use case
set 'esdhc' in hwconfig and save it.
To enable IFC in case of SD boot
a) For temporary use case in runtime without reboot system
run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
b) For long-term use case
set 'ifc' in hwconfig and save it.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb/tlb.c')
| -rw-r--r-- | board/freescale/p1010rdb/tlb.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 77a8043..a7af0f6 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -42,7 +42,6 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SDCARD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), @@ -51,7 +50,6 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1), -#endif #ifdef CONFIG_PCI /* *I*G* - PCI */ @@ -66,7 +64,6 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #endif -#ifndef CONFIG_SDCARD /* *I*G - Board CPLD */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -75,7 +72,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |