diff options
| author | Xu Jiucheng <B37781@freescale.com> | 2013-03-25 07:30:13 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-02 21:57:34 (GMT) |
| commit | 545c12cf9ad16611f3055a097a360bcfab2e6106 (patch) | |
| tree | dbbff93ea2b77a5d118350e7be7fbe9efa5ee521 /board/freescale/p1_p2_rdb_pc/spl_minimal.c | |
| parent | 1f06c9af31a274c8fd1263045d10b5a782fe8e45 (diff) | |
| download | u-boot-545c12cf9ad16611f3055a097a360bcfab2e6106.tar.xz | |
powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC
When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.
Signed-off-by: Xu Jiucheng <B37781@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc/spl_minimal.c')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/spl_minimal.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 09019e9..e2bfb0d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -81,6 +81,8 @@ void board_init_f(ulong bootflag) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#elif defined(CONFIG_P1021RDB) + par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); #endif /* initialize selected port with appropriate baud rate */ @@ -102,6 +104,19 @@ void board_init_f(ulong bootflag) __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); __raw_writel(0x00000000, &pgpio->gpdir); +#elif defined(CONFIG_P1021RDB) + /* init DDR3 reset signal CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00004000); + out_be32(&par_io[1].cpodr, 0x00800000); + out_be32(&par_io[1].cppar1, 0x00000000); + /* reset DDR3 */ + out_be32(&par_io[1].cpdat, 0x00800000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00000000); + udelay(1000); + out_be32(&par_io[1].cpdat, 0x00800000); + /* disable the CE_PB8 */ + out_be32(&par_io[1].cpdir1, 0x00000000); #endif #ifndef CONFIG_SYS_INIT_L2_ADDR |