diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-12-17 08:51:08 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-01-16 17:31:20 (GMT) |
| commit | e26416a3f1631b906776a4e965313b3269faf259 (patch) | |
| tree | 306c0d29a36c15140e64dd7e458f84555e313f78 /board/freescale/t102xrdb/t102xrdb.c | |
| parent | f49b8c1b5d9db6d349000b25312c672a1f6627b8 (diff) | |
| download | u-boot-e26416a3f1631b906776a4e965313b3269faf259.tar.xz | |
powerpc/t1024rdb: Add support for T1024RDB-PB
T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY.
rcw_0x095 is used for 10G XFI + 3x PCIex1
rcw_0x135 is used for 2.5G SGMII + 2x PCIex1
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t102xrdb/t102xrdb.c')
| -rw-r--r-- | board/freescale/t102xrdb/t102xrdb.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 96457cf..e196f12 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -27,6 +27,11 @@ int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", @@ -50,11 +55,34 @@ int checkboard(void) #endif puts("SERDES Reference Clocks:\n"); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + if (srds_s1 == 0x95) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + else + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); return 0; } +static void board_mux_lane(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 reg = CPLD_READ(misc_ctl_status); + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); + } else { + /* Route Lane B to SGMII */ + CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); + } + CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); +} + int board_early_init_f(void) { #if defined(CONFIG_DEEP_SLEEP) @@ -96,6 +124,7 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + board_mux_lane(); return 0; } |