board/freescale: Update ddr clk_adjust

This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5..60ab9ff 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 	{}
 };