powerpc/t2081qds: Add T2081 QDS board support

T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1 files changed, 72 insertions, 0 deletions

diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
new file mode 100644
index 0000000..9fc879a
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	/* TODO: need tuning these parameters if RDIMM is used */
+	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+#endif