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author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-02-21 05:16:19 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2014-02-24 23:23:01 (GMT) |
commit | 254887a57e93a818a10d95451a8ec29cb30c21f4 (patch) | |
tree | 91e95a7fa2c651a77f686cf86599ca773dbd1a0f /board/freescale/t208xqds/law.c | |
parent | 35c471e509465366bbf0b92a589b5cdc69081a7d (diff) | |
download | u-boot-254887a57e93a818a10d95451a8ec29cb30c21f4.tar.xz |
powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xqds/law.c')
-rw-r--r-- | board/freescale/t208xqds/law.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c new file mode 100644 index 0000000..74e2a53 --- /dev/null +++ b/board/freescale/t208xqds/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); |