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authorBin Meng <bmeng.cn@gmail.com>2016-02-06 03:30:11 (GMT)
committerAnatolij Gustschin <agust@denx.de>2016-02-06 11:00:59 (GMT)
commita187559e3d586891c917279044c5386d1b2adc6e (patch)
tree8d50525d0381f28cd41f86e6d8f42ad47d26063e /board/freescale/t4qds
parent94985cc9d3d7ed991ca8b2627d5894df5ea68f49 (diff)
downloadu-boot-a187559e3d586891c917279044c5386d1b2adc6e.tar.xz
Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/freescale/t4qds')
-rw-r--r--board/freescale/t4qds/README18
-rw-r--r--board/freescale/t4qds/eth.c4
2 files changed, 11 insertions, 11 deletions
diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README
index 3962fee..bf23814 100644
--- a/board/freescale/t4qds/README
+++ b/board/freescale/t4qds/README
@@ -86,7 +86,7 @@ Board Features
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-boot
+ introduced to indicate a XFI port will use copper cable, and U-Boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
@@ -118,7 +118,7 @@ The physical address of the last (boot page translation) varies with the actual
Voltage ID and VDD override
--------------------
-T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage
+T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
accordingly. The voltage can also be override by command vdd_override. The
syntax is
@@ -144,8 +144,8 @@ Users can set the final voltage directly.
-------------------------------
PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
SPL further initialise DDR using SPD and environment variables
-and copy u-boot(768 KB) from NAND/SD device to DDR.
-Finally SPL transers control to u-boot for futher booting.
+and copy U-Boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to U-Boot for futher booting.
SPL has following features:
- Executes within 256K
@@ -165,21 +165,21 @@ Run time view of SPL framework
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
-|U-boot SPL | 0xFFFD8000 (160KB) |
+|U-Boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T4QDS
--------------------------------------------------------------
Start End Definition Size
-0x000000 0x0FFFFF u-boot img 1MB
-0x140000 0x15FFFF u-boot env 128KB
+0x000000 0x0FFFFF U-Boot img 1MB
+0x140000 0x15FFFF U-Boot env 128KB
0x160000 0x17FFFF FMAN Ucode 128KB
Micro SD Card memory Map on T4QDS
----------------------------------------------------
Block #blocks Definition Size
-0x008 2048 u-boot img 1MB
-0x800 0016 u-boot env 8KB
+0x008 2048 U-Boot img 1MB
+0x800 0016 U-Boot env 8KB
0x820 0128 FMAN ucode 64KB
Switch Settings: (ON is 1, OFF is 0)
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 83a3a9b..95f8c04 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -658,7 +658,7 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-boot happy */
+ /* A fake PHY address to make U-Boot happy */
fm_info_set_phy_address(i, i);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
@@ -839,7 +839,7 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-boot happy */
+ /* A fake PHY address to make U-Boot happy */
fm_info_set_phy_address(i, i);
} else {
lane = serdes_get_first_lane(FSL_SRDS_2,