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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-05-04 02:20:22 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 21:06:57 (GMT) |
| commit | e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 (patch) | |
| tree | fe6ee40fd32a3abfe8f52b3cf797f5bc3172248b /board/freescale/t4qds | |
| parent | d8e5163ad81a2810c66a9a98e5111769378f5f5f (diff) | |
| download | u-boot-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.tar.xz | |
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/t4qds')
| -rw-r--r-- | board/freescale/t4qds/ddr.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h index 4d0e3c4..0b0cc9a 100644 --- a/board/freescale/t4qds/ddr.h +++ b/board/freescale/t4qds/ddr.h @@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; @@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, {} }; |