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| author | York Sun <york.sun@nxp.com> | 2017-12-05 18:57:54 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-12-26 13:35:59 (GMT) |
| commit | bdc8ea927acfc7c3e4188b0dcf435d39f648989f (patch) | |
| tree | 9be8d2844f7d804ff5d9665c49ecc6b6d91ae942 /board/freescale/t4qds | |
| parent | dac97eb796dd3b9ec2660280b68da5a86a05d4fe (diff) | |
| download | u-boot-bdc8ea927acfc7c3e4188b0dcf435d39f648989f.tar.xz | |
powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/t4qds')
| -rw-r--r-- | board/freescale/t4qds/tlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 1e4d096..a6d8bb3 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif }; |