diff options
| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2014-05-20 05:34:28 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-06-05 19:56:13 (GMT) |
| commit | e6c334a7a4d90b399d2280105146378194b5f5f1 (patch) | |
| tree | a6d1fcda5c7d7c13b3c866498970e995bb2545d0 /board/freescale/t4rdb/eth.c | |
| parent | 40483e1e1d8f87527a1cba37e4641877b890b700 (diff) | |
| download | u-boot-e6c334a7a4d90b399d2280105146378194b5f5f1.tar.xz | |
powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4rdb/eth.c')
| -rw-r--r-- | board/freescale/t4rdb/eth.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index d220475..142c6a8 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis) /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); - if (srds_prtcl_s1 == 28) { + if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { /* SGMII */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); |