diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 13:02:30 (GMT) |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 16:43:50 (GMT) |
commit | 1167a2fd56138b716e01370c4267f3b70bf9ffa0 (patch) | |
tree | 74cfb5d7919a1063de8f7632df44ed81e53c5181 /board/freescale | |
parent | e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e (diff) | |
download | u-boot-1167a2fd56138b716e01370c4267f3b70bf9ffa0.tar.xz |
FSL DDR: Convert MPC8544DS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mpc8544ds/Makefile | 9 | ||||
-rw-r--r-- | board/freescale/mpc8544ds/ddr.c | 80 | ||||
-rw-r--r-- | board/freescale/mpc8544ds/mpc8544ds.c | 11 |
3 files changed, 93 insertions, 7 deletions
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 3a5ea00..3997994 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,10 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c new file mode 100644 index 0000000..bbb5ee2 --- /dev/null +++ b/board/freescale/mpc8544ds/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index c39ce11..4e976b7 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -24,10 +24,11 @@ #include <command.h> #include <pci.h> #include <asm/processor.h> +#include <asm/mmu.h> #include <asm/immap_85xx.h> #include <asm/immap_fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> #include <asm/io.h> -#include <spd_sdram.h> #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> @@ -38,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif -void sdram_init(void); - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -69,7 +68,11 @@ initdram(int board_type) puts("Initializing\n"); - dram_size = spd_sdram(); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* |