diff options
| author | Dirk Eibach <eibach@gdsys.de> | 2011-04-06 11:53:46 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-04-21 08:34:41 (GMT) |
| commit | 5cb4100f5825de5181be1edce8a020bf646a9475 (patch) | |
| tree | 7e08c3969bcb47430a96ee6da75080484b68186e /board/gdsys/405ep/405ep.c | |
| parent | 8aa50540e4e8fe599857db522d58a55469bbb254 (diff) | |
| download | u-boot-5cb4100f5825de5181be1edce8a020bf646a9475.tar.xz | |
ppc4xx: Adapt DLVision 10G to new FPGA firmware
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/gdsys/405ep/405ep.c')
| -rw-r--r-- | board/gdsys/405ep/405ep.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 86a3ec8..8b80533 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -110,6 +110,11 @@ int board_early_init_f(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif /* * wait for fpga out of reset */ @@ -117,9 +122,11 @@ int board_early_init_f(void) while (1) { out_le16(&fpga->reflection_low, REFLECTION_TESTPATTERN); - if (in_le16(&fpga->reflection_high) == + + if (in_le16(reflection_target) == REFLECTION_TESTPATTERN_INV) break; + udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= |