diff options
author | wdenk <wdenk> | 2003-06-27 21:31:46 (GMT) |
---|---|---|
committer | wdenk <wdenk> | 2003-06-27 21:31:46 (GMT) |
commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /board/genietv/genietv.c | |
parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
download | u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.xz |
* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'board/genietv/genietv.c')
-rw-r--r-- | board/genietv/genietv.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c index 8f32ad7..a5e64b3 100644 --- a/board/genietv/genietv.c +++ b/board/genietv/genietv.c @@ -49,9 +49,9 @@ const uint sdram_table[] = /* * SDRAM Initialization (offset 5 in UPMB RAM) * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. * */ 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ @@ -198,21 +198,21 @@ long int initdram (int board_type) if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + - (size_b0 & BR_BA_MSK); + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + + (size_b0 & BR_BA_MSK); } else { - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br2 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ memctl->memc_mptpr = CFG_MPTPR_1BK_4K; } |