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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 10:18:56 (GMT) |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 13:04:04 (GMT) |
| commit | 566ce04de4a2b4c66be8e13751dbb0bfe80117b3 (patch) | |
| tree | 0b9a0f18e8e3a3c97c9adc376056315553343d69 /board/imgtec | |
| parent | 7953354b07bba8fa9599bf5d212308e6cdf9cbe2 (diff) | |
| download | u-boot-566ce04de4a2b4c66be8e13751dbb0bfe80117b3.tar.xz | |
MIPS: Malta: Enable CM & L2 support
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'board/imgtec')
| -rw-r--r-- | board/imgtec/malta/lowlevel_init.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 3d48cdc..6df4d9f 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -28,12 +28,6 @@ .globl lowlevel_init lowlevel_init: - /* disable any L2 cache for now */ - sync - mfc0 t0, CP0_CONFIG, 2 - ori t0, t0, 0x1 << 12 - mtc0 t0, CP0_CONFIG, 2 - /* detect the core card */ PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) |