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| author | Haikun.Wang@freescale.com <Haikun.Wang@freescale.com> | 2015-06-26 11:58:24 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-20 18:44:39 (GMT) |
| commit | 5989df7e2cfb5ac0d8c9a509aad2b84f9141cc13 (patch) | |
| tree | faf63a5ac5615f4bd57f08e84d639dbef2c3cff0 /board/mosaixtech | |
| parent | e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2 (diff) | |
| download | u-boot-5989df7e2cfb5ac0d8c9a509aad2b84f9141cc13.tar.xz | |
armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/mosaixtech')
0 files changed, 0 insertions, 0 deletions