diff options
author | Wolfgang Denk <wd@denx.de> | 2008-05-20 14:00:29 (GMT) |
---|---|---|
committer | Wolfgang Denk <wd@denx.de> | 2008-05-20 22:14:08 (GMT) |
commit | 53677ef18e25c97ac613349087c5cb33ae5a2741 (patch) | |
tree | f947d34d6efaee2401ea0e4c6104ef2f6a0f7ad0 /board/mpl/pip405 | |
parent | 727f63334676e760877d43bfb8f0e9331ac8b101 (diff) | |
download | u-boot-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.xz |
Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/mpl/pip405')
-rw-r--r-- | board/mpl/pip405/cmd_pip405.c | 10 | ||||
-rw-r--r-- | board/mpl/pip405/pip405.h | 20 | ||||
-rw-r--r-- | board/mpl/pip405/u-boot.lds | 8 | ||||
-rw-r--r-- | board/mpl/pip405/u-boot.lds.debug | 8 |
4 files changed, 23 insertions, 23 deletions
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c index 1bf4d7b..945e5c9 100644 --- a/board/mpl/pip405/cmd_pip405.c +++ b/board/mpl/pip405/cmd_pip405.c @@ -38,14 +38,14 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong led_on,led_nr; + ulong led_on,led_nr; if (strcmp(argv[1], "info") == 0) { print_pip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) + return 0; + } + if (strcmp(argv[1], "led") == 0) { led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); led_on = (ulong)simple_strtoul(argv[3], NULL, 10); @@ -54,7 +54,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else user_led1(led_on); return 0; - } + } return (do_mplcommon(cmdtp, flag, argc, argv)); } diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h index b41c5bb..5815786 100644 --- a/board/mpl/pip405/pip405.h +++ b/board/mpl/pip405/pip405.h @@ -56,7 +56,7 @@ void user_led1(unsigned char on); /* timings */ /* CS Config register (CS7) */ -#define CONFIG_PORT_BME 0 /* Burst disable */ +#define CONFIG_PORT_BME 0 /* Burst disable */ #define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ #define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ @@ -67,7 +67,7 @@ void user_led1(unsigned char on); #define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ #define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ #define CONFIG_PORT_PEN 0 /* Parity disable */ -#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ +#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -80,10 +80,10 @@ void user_led1(unsigned char on); /* Flash CS0 or CS 1 */ /* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_BME_B 1 /* Burst enable */ #define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ #define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ +#define FLASH_BME 0 /* Burst disable */ #define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define FLASH_OEN 1 /* Cycles from CS low to OE low */ @@ -95,10 +95,10 @@ void user_led1(unsigned char on); #define FLASH_BEM 0 /* Byte Write only active on Write cycles */ #define FLASH_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -114,10 +114,10 @@ void user_led1(unsigned char on); /* MPS CS1 or CS0 */ /* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ +#define MPS_BME_B 1 /* Burst enable */ #define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ #define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ +#define MPS_BME 0 /* Burst disable */ #define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define MPS_OEN 1 /* Cycles from CS low to OE low */ @@ -129,10 +129,10 @@ void user_led1(unsigned char on); #define MPS_BEM 0 /* Byte Write only active on Write cycles */ #define MPS_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index c7ae4d0..fb71064 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -38,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 88dcaf9..0552994 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } |