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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-02 01:40:26 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-09-02 15:33:15 (GMT) |
| commit | 242836a893ae8bce4bd3cd4ace8a55e48e6552a0 (patch) | |
| tree | 3d17ecb6a9354cdbe0074cf13bd46208ff4ffbe6 /board/pcs440ep/init.S | |
| parent | c6999e5f85ec41b8a5d01d7b3e311eda832fc218 (diff) | |
| download | u-boot-242836a893ae8bce4bd3cd4ace8a55e48e6552a0.tar.xz | |
powerpc: ppc4xx: remove pcs440ep support
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/pcs440ep/init.S')
| -rw-r--r-- | board/pcs440ep/init.S | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S deleted file mode 100644 index c0e83de..0000000 --- a/board/pcs440ep/init.S +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR detection - * routine. - */ - - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) - - /* USB 2.0 Device */ - tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) - - tlbtab_end |