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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-08-05 22:47:06 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-13 20:06:02 (GMT) |
| commit | adf4800d8570a1212be329ab6fcead4c284ede89 (patch) | |
| tree | 5d0766efad295f9ba7feab8ba4e3fbab12149ea0 /board/qemu-mips | |
| parent | 1bc66a57c067eba5f687c2ab0a70956821dc7220 (diff) | |
| download | u-boot-adf4800d8570a1212be329ab6fcead4c284ede89.tar.xz | |
mtd/nand/tegra: alignment workaround
Integrate cache alignment bounce buffer to workaround issues as follows:
Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Done
Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ]
Starting kernel ...
undefined instruction
pc : [<005ff03c>] lr : [<0000800c>]
sp : 0144b6e8 ip : 01000188 fp : 0144a6c8
r10: 00000000 r9 : 411fc090 r8 : 00000100
r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000
r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/qemu-mips')
0 files changed, 0 insertions, 0 deletions