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| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2016-03-31 18:51:33 (GMT) |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2016-08-17 01:25:35 (GMT) |
| commit | a7da6f8c3d6d685af9426cdc2357d2e66cff2875 (patch) | |
| tree | 4ad21723e23975c87283a12b23a41d1277816e43 /board/renesas/rcar-common | |
| parent | 7a500a7a78002b470800794f615b8dca251816c7 (diff) | |
| download | u-boot-a7da6f8c3d6d685af9426cdc2357d2e66cff2875.tar.xz | |
ARM: rmobile: Move rcar-gen2-common to rcar-common
To common use of rcar-gen2-common directory in the R-Car SoCs, and change from
rcar-gen2-common to rcar-common.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/rcar-common')
| -rw-r--r-- | board/renesas/rcar-common/common.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c new file mode 100644 index 0000000..be2b945 --- /dev/null +++ b/board/renesas/rcar-common/common.c @@ -0,0 +1,59 @@ +/* + * board/renesas/rcar-common/common.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#define TSTR0 0x04 +#define TSTR0_STR0 0x01 + +static struct mstp_ctl mstptbl[] = { + { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, + RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, + { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, + { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, + RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, + { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, + RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, + { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, + RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, + { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, + RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, + /* No MSTP6 */ + { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, + RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, + { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, + RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, + { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, + RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, + { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, + RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, + { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, +}; + +void arch_preboot_os(void) +{ + int i; + + /* stop TMU0 */ + mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); + + /* Stop module clock */ + for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { + mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis, + mstptbl[i].s_ena); + mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis, + mstptbl[i].r_ena); + } +} |