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authorPaul Gortmaker <paul.gortmaker@windriver.com>2011-12-31 04:53:10 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2012-01-11 19:59:07 (GMT)
commit7e44f2b710db09a1b02e55246e0915732cc4775e (patch)
treee94b2b4fa41c941841bcb5b61214e3b9b82f12d3 /board/sbc8548
parent5f4c6f0db930646e9ca3b479b5fe9b8d2691fa77 (diff)
downloadu-boot-7e44f2b710db09a1b02e55246e0915732cc4775e.tar.xz
sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548')
-rw-r--r--board/sbc8548/law.c5
-rw-r--r--board/sbc8548/tlb.c2
2 files changed, 7 insertions, 0 deletions
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index c263191..322af76 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -59,8 +59,13 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+ /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 4bf7214..af927f1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/*
* TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
@@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
/*
* TLB 5: 16M Cacheable, non-guarded