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authorBecky Bruce <beckyb@kernel.crashing.org>2010-06-17 16:37:20 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 15:55:09 (GMT)
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /board/sheldon/simpc8313/sdram.c
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
downloadu-boot-f51cdaf19141151ce2b40d562a468605340f2315.tar.xz
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sheldon/simpc8313/sdram.c')
-rw-r--r--board/sheldon/simpc8313/sdram.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c
index ebb70a2..ba59943 100644
--- a/board/sheldon/simpc8313/sdram.c
+++ b/board/sheldon/simpc8313/sdram.c
@@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc= &im->lbus;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)