diff options
author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 13:01:15 (GMT) |
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committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 19:54:03 (GMT) |
commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/siemens/CCM | |
parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
download | u-boot-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.xz |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/siemens/CCM')
-rw-r--r-- | board/siemens/CCM/ccm.c | 80 | ||||
-rw-r--r-- | board/siemens/CCM/flash.c | 38 | ||||
-rw-r--r-- | board/siemens/CCM/fpga_ccm.c | 4 |
3 files changed, 61 insertions, 61 deletions
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index d653763..8053da4 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -133,7 +133,7 @@ int checkboard (void) int power_on_reset(void) { /* Test Reset Status Register */ - return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; + return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; } #define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ @@ -142,7 +142,7 @@ int power_on_reset(void) static void init_leds (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_cpm.cp_pbpar &= ~PB_LEDS; immap->im_cpm.cp_pbodr &= ~PB_LEDS; @@ -157,7 +157,7 @@ static void init_leds (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size = 0; @@ -171,7 +171,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -180,10 +180,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay(200); @@ -203,21 +203,21 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size = size9; /* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay(500); /* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ } @@ -230,7 +230,7 @@ phys_size_t initdram (int board_type) */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay(1000); } @@ -238,13 +238,13 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; can_driver_enable (); @@ -263,7 +263,7 @@ phys_size_t initdram (int board_type) */ void can_driver_enable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Initialize MBMR */ @@ -302,13 +302,13 @@ void can_driver_enable (void) memctl->memc_mcr = 0x011C | UPMB; /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; } void can_driver_disable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Reset OR3 / BR3 to disable CAN Bus Controller */ @@ -331,7 +331,7 @@ void can_driver_disable (void) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -341,24 +341,24 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize /* ------------------------------------------------------------------------- */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN) +#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) void reset_phy(void) { - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ulong value; /* Configure all needed port pins for GPIO */ -#ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +#ifdef CONFIG_SYS_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; #else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ #endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ @@ -366,23 +366,23 @@ void reset_phy(void) value = immr->im_cpm.cp_pbdat; /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; + value |= CONFIG_SYS_PB_ETH_POWERDOWN; /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; +#ifdef CONFIG_SYS_ETH_CFG1_VALUE + value |= CONFIG_SYS_PB_ETH_CFG1; #else - value &= ~(CFG_PB_ETH_CFG1); + value &= ~(CONFIG_SYS_PB_ETH_CFG1); #endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; +#ifdef CONFIG_SYS_ETH_CFG2_VALUE + value |= CONFIG_SYS_PB_ETH_CFG2; #else - value &= ~(CFG_PB_ETH_CFG2); + value &= ~(CONFIG_SYS_PB_ETH_CFG2); #endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; +#ifdef CONFIG_SYS_ETH_CFG3_VALUE + value |= CONFIG_SYS_PB_ETH_CFG3; #else - value &= ~(CFG_PB_ETH_CFG3); + value &= ~(CONFIG_SYS_PB_ETH_CFG3); #endif /* Drive output signals to initial state */ @@ -391,11 +391,11 @@ void reset_phy(void) udelay (10000); /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (10000); /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET; + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; udelay (1000); } diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c index 9c32785..ad1ed79 100644 --- a/board/siemens/CCM/flash.c +++ b/board/siemens/CCM/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,38 +75,38 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif } else { @@ -419,7 +419,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -542,7 +542,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c index 11b97bc..50b08ab 100644 --- a/board/siemens/CCM/fpga_ccm.c +++ b/board/siemens/CCM/fpga_ccm.c @@ -31,7 +31,7 @@ fpga_t fpga_list[] = { { "PUMA" , PUMA_CONF_BASE , - CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE } + CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } }; int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); @@ -90,7 +90,7 @@ const uint puma_table[] = ulong fpga_control (fpga_t* fpga, int cmd) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; switch (cmd) { |