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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2014-11-13 17:08:18 (GMT) |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-11-17 10:03:38 (GMT) |
| commit | 061091098a5ec55ff4b68b61592af8619c2c7d88 (patch) | |
| tree | b5339bc118f1e114d79713dc0e6bf5022e025085 /board/teejet | |
| parent | 79043d84da076e4eb47e04495c55216897c9a161 (diff) | |
| download | u-boot-061091098a5ec55ff4b68b61592af8619c2c7d88.tar.xz | |
DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/teejet')
0 files changed, 0 insertions, 0 deletions