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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-05-04 02:20:22 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 21:06:57 (GMT) |
| commit | e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 (patch) | |
| tree | fe6ee40fd32a3abfe8f52b3cf797f5bc3172248b /board/terasic | |
| parent | d8e5163ad81a2810c66a9a98e5111769378f5f5f (diff) | |
| download | u-boot-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.tar.xz | |
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/terasic')
0 files changed, 0 insertions, 0 deletions