diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-11-30 21:41:55 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-12-16 08:56:38 (GMT) |
| commit | 9e73c1b7d11611d51f0026d375731f0316dd26e8 (patch) | |
| tree | 0803c5f8cfa397cbb2c0f90c6c19b55ae336946a /board/toradex | |
| parent | 6119b0f764eb8b68d6148d4c017cbd343408c2d8 (diff) | |
| download | u-boot-9e73c1b7d11611d51f0026d375731f0316dd26e8.tar.xz | |
colibri_vf: cleanup USB clock initialization
Use the same preprocessor define to enable clocks as we use to
enable the driver. Make sure that the necessary PLL's are on
(they get enabled by boot ROM by default, so this is more for
completness).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'board/toradex')
| -rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 0f8b440..15f263c 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -368,12 +368,18 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK); -#ifdef CONFIG_CI_UDC +#ifdef CONFIG_USB_EHCI_VF setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); -#endif - -#ifdef CONFIG_USB_EHCI setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); + + clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | + ANADIG_PLL3_CTRL_POWERDOWN | + ANADIG_PLL3_CTRL_DIV_SELECT, + ANADIG_PLL3_CTRL_ENABLE); + clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | + ANADIG_PLL7_CTRL_POWERDOWN | + ANADIG_PLL7_CTRL_DIV_SELECT, + ANADIG_PLL7_CTRL_ENABLE); #endif clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | |