diff options
author | Wolfgang Grandegger <wg@grandegger.com> | 2008-06-04 11:52:17 (GMT) |
---|---|---|
committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-06-10 23:22:26 (GMT) |
commit | 4677988c7edc070c3786d3db7994abeca3ab82a0 (patch) | |
tree | afe5291cc036cf5718f23734d1133cc71e26e5e0 /board/tqc/tqm5200 | |
parent | 6fab2fe72ca5bf95280cd52cdf378af3e506eb50 (diff) | |
download | u-boot-4677988c7edc070c3786d3db7994abeca3ab82a0.tar.xz |
TQM: move TQM boards to board/tqc
Move all TQM board directories to the vendor specific directory "tqc"
for modules from TQ-Components GmbH (http://www.tqc.de).
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'board/tqc/tqm5200')
-rw-r--r-- | board/tqc/tqm5200/Makefile | 53 | ||||
-rw-r--r-- | board/tqc/tqm5200/cam5200_flash.c | 786 | ||||
-rw-r--r-- | board/tqc/tqm5200/cmd_stk52xx.c | 1247 | ||||
-rw-r--r-- | board/tqc/tqm5200/cmd_tb5200.c | 104 | ||||
-rw-r--r-- | board/tqc/tqm5200/config.mk | 46 | ||||
-rw-r--r-- | board/tqc/tqm5200/mt48lc16m16a2-75.h | 47 | ||||
-rw-r--r-- | board/tqc/tqm5200/tqm5200.c | 751 |
7 files changed, 3034 insertions, 0 deletions
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile new file mode 100644 index 0000000..a5ce7bd --- /dev/null +++ b/board/tqc/tqm5200/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +cam5200_flash.o: cam5200_flash.c + $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $< + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c new file mode 100644 index 0000000..b3f095d --- /dev/null +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -0,0 +1,786 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <asm/processor.h> + +#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) + +#if 0 +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif + +#define swap16(x) __swab16(x) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CAM5200 is a TQM5200B based board. Additionally it also features + * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx + * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as + * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes + * access to flash chip slightly more complicated as additional byte + * swapping is necessary within each 16 bit wide flash 'word'. + * + * This driver's task is to handle both flash devices: 32 bit TQM5200B + * flash chip and 16 bit NIOS cpu flash chip. In the below + * flash_addr_table table we use least significant address bit to mark + * 16 bit flash bank and two sets of routines *_32 and *_16 to handle + * specifics of both flashes. + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {CFG_BOOTCS_START, CFG_CS5_START | 1} +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_32(flash_info_t * info, ulong dest, ulong data); +static int write_word_16(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_32(flash_info_t * info, int s_first, int s_last); +static int flash_erase_16(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_32(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_16(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i, k; + int size, erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_S29GL128N: + printf ("S29GL128N (256 Mbit, uniform sector size)\n"); + break; + case FLASH_AM320B: + printf ("29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("29LV320T (32 Mbit, top boot sect)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + + printf(" %08lX%s%s", info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + + DEBUGF("get_size: FLASH ADDR %08lx\n", addr); + + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) + return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info); + else + return flash_get_size_32(addr, info); +} + +static ulong flash_get_size_32(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case AMD_ID_MIRROR: + DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + switch(addr[14]) { + case AMD_ID_GL128N_2: + if (addr[15] != AMD_ID_GL128N_3) { + DEBUGF("Chip: S29GL128N -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + DEBUGF("Chip: S29GL128N\n"); + info->flash_id += FLASH_S29GL128N; + info->sector_count = 128; + info->size = 0x02000000; + } + break; + default: + info->flash_id = FLASH_UNKNOWN; + return(0); + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00040000); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_32(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { + return flash_erase_16(info, s_first, s_last); + } else { + return flash_erase_32(info, s_first, s_last); + } +} + +static int flash_erase_32(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_32(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) + data = (data << 8) | *src++; + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + cnt -= 4; + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { + return write_word_16(info, dest, data); + } else { + return write_word_32(info, dest, data); + } +} + +static int write_word_32(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i, flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000; + udelay(1000); + + value = swap16(addr2[0]); + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = swap16(addr2[1]); /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000a000; + info->start[6] = base + 0x0000c000; + info->start[7] = base + 0x0000e000; + + for (i = 8; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; + + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + + return (info->size); +} + +static int wait_for_DQ7_16(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) != + (CFG_FLASH_WORD_SIZE) 0x80008000) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_16(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ + + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_16(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_16(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000; + + dest2[i] = swap16(data2[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) != + (swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) + continue; + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + + flash_info[i].size = size_b[i]; + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i+1, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + total_b += flash_info[i].size; + } + + return total_b; +} +#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */ diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c new file mode 100644 index 0000000..7472ca9 --- /dev/null +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -0,0 +1,1247 @@ +/* + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * STK52XX specific functions + */ +/*#define DEBUG*/ + +#include <common.h> +#include <command.h> + +#if defined(CONFIG_CMD_BSP) + +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) +#define DEFAULT_VOL 45 +#define DEFAULT_FREQ 500 +#define DEFAULT_DURATION 200 +#define LEFT 1 +#define RIGHT 2 +#define LEFT_RIGHT 3 +#define BL_OFF 0 +#define BL_ON 1 + +#define SM501_GPIO_CTRL_LOW 0x00000008UL +#define SM501_GPIO_CTRL_HIGH 0x0000000CUL +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel); +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel); +static void spi_init(void); +static int spi_transmit(unsigned char data); +static void pcm1772_write_reg(unsigned char addr, unsigned char data); +static void set_attenuation(unsigned char attenuation); + +static void spi_init(void) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* PSC3 as SPI and GPIOs */ + gpio->port_config &= 0xFFFFF0FF; + gpio->port_config |= 0x00000800; + /* + * Its important to use the correct order when initializing the + * registers + */ + spi->ddr = 0x0F; /* set all SPI pins as output */ + spi->pdr = 0x08; /* set SS high */ + spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ + spi->cr2 = 0x00; /* normal operation */ + spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ +} + +static int spi_transmit(unsigned char data) +{ + int dummy; + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->dr = data; + /* wait for SPI transmission completed */ + while(!(spi->sr & 0x80)) + { + if (spi->sr & 0x40) /* if write collision occured */ + { + /* do dummy read to clear status register */ + dummy = spi->dr; + printf ("SPI write collision\n"); + return -1; + } + } + return (spi->dr); +} + +static void pcm1772_write_reg(unsigned char addr, unsigned char data) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->pdr = 0x00; /* Set SS low */ + spi_transmit(addr); + spi_transmit(data); + /* wait some time to meet MS# hold time of PCM1772 */ + udelay (1); + spi->pdr = 0x08; /* set SS high */ +} + +static void set_attenuation(unsigned char attenuation) +{ + pcm1772_write_reg(0x01, attenuation); /* left channel */ + debug ("PCM1772 attenuation left set to %d.\n", attenuation); + pcm1772_write_reg(0x02, attenuation); /* right channel */ + debug ("PCM1772 attenuation right set to %d.\n", attenuation); +} + +void amplifier_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* Do this only once, because of the long time delay */ + if (!init_done) { + /* configure PCM1772 audio format as I2S */ + pcm1772_write_reg(0x03, 0x01); + /* enable audio amplifier */ + gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ + gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ + gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ + gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ + /* + * wait some time to allow amplifier to recover from shutdown + * mode. + */ + for(i = 0; i < 350; i++) + udelay(1000); + /* + * The used amplifier (LM4867) has a so called "pop and click" + * elmination filter. The input signal of the amplifier must + * exceed a certain level once after power up to activate the + * generation of the output signal. This is achieved by + * sending a low frequent (nearly inaudible) sawtooth with a + * sufficient signal level. + */ + set_attenuation(50); + i2s_sawtooth (200, 5, LEFT_RIGHT); + init_done = 1; + } +} + +static void i2s_init(void) +{ + unsigned long i; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + psc->sicr = 0x22E00000; /* 16 bit data; I2S */ + + *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK + * 5.617 MHz */ + *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable + * register */ + psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ + psc->ctur = 0x0F; /* 16 bit frame width */ + + for(i=0;i<128;i++) + { + psc->psc_buffer_32 = 0; /* clear tx fifo */ + } +} + +static int i2s_play_wave(unsigned long addr, unsigned long len) +{ + unsigned long i; + unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip + * wav header*/ + unsigned char swapped[4]; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + /* + * play wave file in memory; bytes/words are be swapped + */ + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + for(i = 0;i < (len / 4); i++) { + swapped[3]=*wave_file++; + swapped[2]=*wave_file++; + swapped[1]=*wave_file++; + swapped[0]=*wave_file++; + psc->psc_buffer_32 = *((unsigned long*)swapped); + while (psc->tfnum > 400) { + if(ctrlc()) + return 0; + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + return 0; +} + +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sawtooth. Start with middle level up to highest level. Then + * go to lowest level and back to middle level. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sqarewave. Start with high level, duty cycle 1:1. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x7FFF; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x8000; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long reg, val, duration; + char *tmp; + unsigned int freq, channel; + unsigned char volume; + int rcode = 1; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1],"saw",3) == 0) { + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + printf ("Play squarewave\n"); + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 4: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strcmp(argv[1],"pcm1772") == 0) { + reg = simple_strtoul(argv[2], NULL, 10); + val = simple_strtoul(argv[3], NULL, 10); + printf("Set PCM1772 %lu. %lu\n", reg, val); + pcm1772_write_reg((uchar)reg, (uchar)val); + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 5: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_sawtooth (duration, freq, + channel); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + channel); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); + return 1; +} + +static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long length, addr; + unsigned char volume; + int rcode = 1; + char *tmp; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + switch (argc) { + + case 3: + length = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); + break; + + case 2: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + addr = simple_strtoul(argv[1], NULL, 16); + + case 1: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + if ((tmp = getenv ("loadaddr")) != NULL) { + addr = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No loadaddr provided\n"); + return 1; + } + break; + + default: + printf("Usage:\nwav <addr> <length[s]\n"); + return 1; + break; + } + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + printf("Play wave file at %#p with length %#x\n", addr, length); + rcode = i2s_play_wave(addr, length); + + return rcode; +} + +static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char volume; + unsigned int channel; + int rcode; + char *tmp; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + switch (argc) { + case 0: + case 1: + channel = LEFT_RIGHT; + break; + case 2: + if (strncmp(argv[1],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[1],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + printf("Beep on "); + if (channel == LEFT) + printf ("left "); + else if (channel == RIGHT) + printf ("right "); + else + printf ("left and right "); + printf ("channel\n"); + + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel); + + return rcode; +} +#endif + +#if defined(CONFIG_STK52XX) +void led_init(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure PSC3 for SPI and GPIO */ + gpio->port_config &= ~(0x00000F00); + gpio->port_config |= 0x00000800; + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + + /* configure timer 4-7 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; + gpt->gpt5.emsr |= 0x00000024; + gpt->gpt6.emsr |= 0x00000024; + gpt->gpt7.emsr |= 0x00000024; + +#ifndef CONFIG_TQM5200S + /* enable SM501 GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + + /* configure SM501 gpio pins 24-27 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); + + /* configure SM501 gpio pins 48-51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); +#endif /* !CONFIG_TQM5200S */ +} + +/* + * return 1 if led number unknown + * return 0 else + */ +int do_led(char *argv[]) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 0: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 8); + } else { + gpio->simple_dvo &= ~(1 << 8); + } + break; + + case 1: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 9); + } else { + gpio->simple_dvo &= ~(1 << 9); + } + break; + + case 2: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 10); + } else { + gpio->simple_dvo &= ~(1 << 10); + } + break; + + case 3: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 11); + } else { + gpio->simple_dvo &= ~(1 << 11); + } + break; + + case 4: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt4.emsr |= (1 << 4); + } else { + gpt->gpt4.emsr &= ~(1 << 4); + } + break; + + case 5: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt5.emsr |= (1 << 4); + } else { + gpt->gpt5.emsr &= ~(1 << 4); + } + break; + + case 6: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt6.emsr |= (1 << 4); + } else { + gpt->gpt6.emsr &= ~(1 << 4); + } + break; + + case 7: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt7.emsr |= (1 << 4); + } else { + gpt->gpt7.emsr &= ~(1 << 4); + } + break; +#ifndef CONFIG_TQM5200S + case 24: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 24); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 24); + } + break; + + case 25: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 25); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 25); + } + break; + + case 26: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 26); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 26); + } + break; + + case 27: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 27); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 27); + } + break; + + case 48: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 16); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 16); + } + break; + + case 49: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 17); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 17); + } + break; + + case 50: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 18); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 18); + } + break; + + case 51: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 19); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 19); + } + break; +#endif /* !CONFIG_TQM5200S */ + default: + printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); + return 1; + } + + return 0; +} +#endif + +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) +/* + * return 1 on CAN initialization failure + * return 0 if no failure + */ +int can_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* GPIO configuration of the CAN pins is done in TQM5200.h */ + + if (!init_done) { + /* init CAN 1 */ + can1->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can1->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can1->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can1->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can1->canctl1 = 0x80; + can1->canctl1 |= 0x40; + can1->canbtr0 = 0x0F; + can1->canbtr1 = 0x7F; + can1->canidac &= ~(0x30); + can1->canidar1 = 0x00; + can1->canidar3 = 0x00; + can1->canidar5 = 0x00; + can1->canidar7 = 0x00; + can1->canidmr0 = 0xFF; + can1->canidmr1 = 0xFF; + can1->canidmr2 = 0xFF; + can1->canidmr3 = 0xFF; + can1->canidmr4 = 0xFF; + can1->canidmr5 = 0xFF; + can1->canidmr6 = 0xFF; + can1->canidmr7 = 0xFF; + + i = 0; + can1->canctl0 &= ~(0x01); /* leave init mode */ + can1->canctl0 &= ~(0x02); + /* wait until init and sleep mode left */ + while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + + /* init CAN 2 */ + can2->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can2->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can2->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can2->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can2->canctl1 = 0x80; + can2->canctl1 |= 0x40; + can2->canbtr0 = 0x0F; + can2->canbtr1 = 0x7F; + can2->canidac &= ~(0x30); + can2->canidar1 = 0x00; + can2->canidar3 = 0x00; + can2->canidar5 = 0x00; + can2->canidar7 = 0x00; + can2->canidmr0 = 0xFF; + can2->canidmr1 = 0xFF; + can2->canidmr2 = 0xFF; + can2->canidmr3 = 0xFF; + can2->canidmr4 = 0xFF; + can2->canidmr5 = 0xFF; + can2->canidmr6 = 0xFF; + can2->canidmr7 = 0xFF; + can2->canctl0 &= ~(0x01); /* leave init mode */ + can2->canctl0 &= ~(0x02); + + i = 0; + /* wait until init mode left */ + while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + init_done = 1; + } + return 0; +} + +/* + * return 1 on CAN failure + * return 0 if no failure + */ +int do_can(char *argv[]) +{ + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* send a message on CAN1 */ + can1->cantbsel = 0x01; + can1->cantxfg.idr[0] = 0x55; + can1->cantxfg.idr[1] = 0x00; + can1->cantxfg.idr[1] &= ~0x8; + can1->cantxfg.idr[1] &= ~0x10; + can1->cantxfg.dsr[0] = 0xCC; + can1->cantxfg.dlr = 1; + can1->cantxfg.tbpr = 0; + can1->cantflg = 0x01; + + i = 0; + while ((can1->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN1 send timeout, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can2->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN2 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can2->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN2 receive error, " + "data mismatch!\n", + __FUNCTION__); + return 1; + } + + /* send a message on CAN2 */ + can2->cantbsel = 0x01; + can2->cantxfg.idr[0] = 0x55; + can2->cantxfg.idr[1] = 0x00; + can2->cantxfg.idr[1] &= ~0x8; + can2->cantxfg.idr[1] &= ~0x10; + can2->cantxfg.dsr[0] = 0xCC; + can2->cantxfg.dlr = 1; + can2->cantxfg.tbpr = 0; + can2->cantflg = 0x01; + + i = 0; + while ((can2->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN2 send error, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can1->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN1 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can1->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN1 receive error 0x%02x\n", + __FUNCTION__, (can1->canrxfg.dsr[0])); + return 1; + } + + return 0; +} + +/* + * return 1 if rs232 port unknown + * return 2 on txd/rxd failure (only rs232 2) + * return 3 on rts/cts failure + * return 0 if no failure + */ +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + break; + + case 2: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + break; + + default: + printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + + return error_status; +} + +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) +static void sm501_backlight (unsigned int state) +{ + if (state == BL_ON) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == BL_OFF) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif +#if defined(CONFIG_STK52XX) + led_init(); +#endif + can_init(); + + switch (argc) { + + case 0: + case 1: + break; + + case 2: + if (strncmp (argv[1], "can", 3) == 0) { + rcode = do_can (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; + } + break; + + case 3: + if (strncmp (argv[1], "rs232", 3) == 0) { + rcode = do_rs232 (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; +#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) + } else if (strncmp (argv[1], "backlight", 4) == 0) { + if (strncmp (argv[2], "on", 2) == 0) { + sm501_backlight (BL_ON); + return 0; + } + else if (strncmp (argv[2], "off", 3) == 0) { + sm501_backlight (BL_OFF); + return 0; + } +#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ + } + break; + +#if defined(CONFIG_STK52XX) + case 4: + if (strcmp (argv[1], "led") == 0) { + return (do_led (argv)); + } + break; +#endif + + default: + break; + } + + printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); + return 1; +} + + +U_BOOT_CMD( + sound , 5, 1, cmd_sound, + "sound - Sound sub-system\n", + "saw [duration] [freq] [channel]\n" + " - generate sawtooth for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "sound square [duration] [freq] [channel]\n" + " - generate squarewave for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "pcm1772 reg val\n" +); + +U_BOOT_CMD( + wav , 3, 1, cmd_wav, + "wav - play wav file\n", + "[addr] [bytes]\n" + " - play wav file at address 'addr' with length 'bytes'\n" +); + +U_BOOT_CMD( + beep , 2, 1, cmd_beep, + "beep - play short beep\n", + "[channel]\n" + " - play short beep on \"l\"eft or \"r\"ight channel\n" +); +#endif /* CONFIG_STK52XX || CONFIG_FO300 */ + +#if defined(CONFIG_STK52XX) +U_BOOT_CMD( + fkt , 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "led number on/off\n" + " - 'number's like printed on STK52XX board\n" + "fkt can\n" + " - loopback plug for X83 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X2 required\n" +#ifndef CONFIG_TQM5200S + "fkt backlight on/off\n" + " - switch backlight on or off\n" +#endif /* !CONFIG_TQM5200S */ +); +#elif defined(CONFIG_FO300) +U_BOOT_CMD( + fkt , 3, 1, cmd_fkt, + "fkt - Function test routines\n", + "fkt can\n" + " - loopback plug for X16/X29 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X21/X22 required\n" +); +#endif +#endif diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c new file mode 100644 index 0000000..214dca6 --- /dev/null +++ b/board/tqc/tqm5200/cmd_tb5200.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2005 - 2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TB5200 specific functions + */ +/*#define DEBUG*/ + +#include <common.h> +#include <command.h> + +#if defined(CONFIG_CMD_BSP) +#if defined (CONFIG_TB5200) + +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static void led_init(void) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure timer 4 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; +} + +int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + led_init(); + + if (strcmp (argv[1], "on") == 0) { + debug ("switch status LED on\n"); + gpt->gpt4.emsr |= (1 << 4); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch status LED off\n"); + gpt->gpt4.emsr &= ~(1 << 4); + } else { + printf ("Usage:\nled on/off\n"); + return 1; + } + + return 0; +} + +static void sm501_backlight (unsigned int state) +{ + if (state == 1) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == 0) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} + +int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (strcmp (argv[1], "on") == 0) { + debug ("switch backlight on\n"); + sm501_backlight (1); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch backlight off\n"); + sm501_backlight (0); + } else { + printf ("Usage:\nbacklight on/off\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + led , 2, 1, cmd_led, + "led - switch status LED on or off\n", + "on/off\n" +); + +U_BOOT_CMD( + backlight , 2, 1, cmd_backlight, + "backlight - switch backlight on or off\n", + "on/off\n" + ); + +#endif /* CONFIG_STK52XX */ +#endif diff --git a/board/tqc/tqm5200/config.mk b/board/tqc/tqm5200/config.mk new file mode 100644 index 0000000..d72dfe7 --- /dev/null +++ b/board/tqc/tqm5200/config.mk @@ -0,0 +1,46 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM5200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFC000000 boot low (standard configuration with room for max 64 MByte +# Flash ROM) +# 0xFFF00000 boot high (for a backup copy of U-Boot) +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFC000000 +## For a backup copy of U-Boot at the end of flash: boot high +# TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..3f1e169 --- /dev/null +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c new file mode 100644 index 0000000..f9891db --- /dev/null +++ b/board/tqc/tqm5200/tqm5200.c @@ -0,0 +1,751 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm/processor.h> +#include <libfdt.h> + +#ifdef CONFIG_VIDEO_SM501 +#include <sm501.h> +#endif + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifdef CONFIG_OF_LIBFDT +#include <fdt_support.h> +#endif /* CONFIG_OF_LIBFDT */ + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; + +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + +#if defined(CONFIG_TQM5200_B) + return dramsize + dramsize2; +#else + return dramsize; +#endif /* CONFIG_TQM5200_B */ +} + +int checkboard (void) +{ +#if defined(CONFIG_AEVFIFO) + puts ("Board: AEVFIFO\n"); + return 0; +#endif + +#if defined(CONFIG_TQM5200S) +# define MODULE_NAME "TQM5200S" +#else +# define MODULE_NAME "TQM5200" +#endif + +#if defined(CONFIG_STK52XX) +# define CARRIER_NAME "STK52xx" +#elif defined(CONFIG_TB5200) +# define CARRIER_NAME "TB5200" +#elif defined(CONFIG_CAM5200) +# define CARRIER_NAME "CAM5200" +#elif defined(CONFIG_FO300) +# define CARRIER_NAME "FO300" +#else +# error "UNKNOWN" +#endif + + puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" + " on a " CARRIER_NAME " carrier board\n"); + + return 0; +} + +#undef MODULE_NAME +#undef CARRIER_NAME + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +#if defined (CONFIG_MINIFAP) +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_51 0x00080000UL +#endif /* CONFIG MINIFAP */ + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +#if defined (CONFIG_MINIFAP) + /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ + + /* enable GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + /* configure GPIO51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= + SM501_GPIO_51; +#else + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + + /* by default the ATA reset is de-asserted */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; +#endif +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +#if defined (CONFIG_MINIFAP) + if (idereset) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~SM501_GPIO_51; + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + SM501_GPIO_51; + } +#else + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } +#endif +} +#endif + +#ifdef CONFIG_POST +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ +#ifdef CONFIG_STK52XX + struct mpc5xxx_gpio *gpio; + + gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + gpio->port_config &= ~(0x07000000); + gpio->port_config |= 0x03000000; + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + gpio->simple_gpioe |= 0x20000000; + + /* Configure GPIO_IRDA_1 as input */ + gpio->simple_ddr &= ~(0x20000000); + + return ((gpio->simple_ival & 0x20000000) ? 0 : 1); +#else + return 0; +#endif +} +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + + extern int usb_cpu_init(void); + +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) + /* Low level USB init, required for proper kernel operation */ + usb_cpu_init(); +#endif + + return (0); +} +#endif + +#ifdef CONFIG_FO300 +int silent_boot (void) +{ + vu_long timer3_status; + + /* Configure GPT3 as GPIO input */ + *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; + + /* Read in TIMER_3 pin status */ + timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; + +#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED + /* Force silent console mode if S1 switch + * is in closed position (TIMER_3 pin status is LOW). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) + return 1; +#else + /* Force silent console mode if S1 switch + * is in open position (TIMER_3 pin status is HIGH). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) + return 1; +#endif + + return 0; +} + +int board_early_init_f (void) +{ + if (silent_boot()) + gd->flags |= GD_FLG_SILENT; + + return 0; +} +#endif /* CONFIG_FO300 */ + +int last_stage_init (void) +{ + /* + * auto scan for really existing devices and re-set chip select + * configuration. + */ + u16 save, tmp; + int restore; + + /* + * Check for SRAM and SRAM size + */ + + /* save original SRAM content */ + save = *(volatile u16 *)CFG_CS2_START; + restore = 1; + + /* write test pattern to SRAM */ + *(volatile u16 *)CFG_CS2_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in SRAM detection\n"); + + if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + /* no SRAM at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + /* make sure that we access a mirrored address */ + *(volatile u16 *)CFG_CS2_START = 0x1111; + __asm__ volatile ("sync"); + if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + /* SRAM size = 512 kByte */ + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + 0x80000); + __asm__ volatile ("sync"); + puts ("SRAM: 512 kB\n"); + } + else + puts ("!! possible error in SRAM detection\n"); + } else { + puts ("SRAM: 1 MB\n"); + } + /* restore origianl SRAM content */ + if (restore) { + *(volatile u16 *)CFG_CS2_START = save; + __asm__ volatile ("sync"); + } + +#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else { + puts ("VGA: SMI501 (Voyager) with 8 MB\n"); + } + /* restore origianl FB content */ + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + +#ifdef CONFIG_FO300 + if (silent_boot()) { + setenv("bootdelay", "0"); + disable_ctrlc(1); + } +#endif +#endif /* !CONFIG_TQM5200S */ + + return 0; +} + +#ifdef CONFIG_VIDEO_SM501 + +#ifdef CONFIG_FO300 +#define DISPLAY_WIDTH 800 +#else +#define DISPLAY_WIDTH 640 +#endif +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#error CONFIG_VIDEO_SM501_16BPP not supported. +#endif /* CONFIG_VIDEO_SM501_16BPP */ +#ifdef CONFIG_VIDEO_SM501_32BPP +static const SMI_REGS init_regs [] = +{ +#if 0 /* CRT only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x10090a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x10090a01}, + {0x00054, 0x0}, + {0x80200, 0x00010000}, + {0x80204, 0x0}, + {0x80208, 0x0A000A00}, + {0x8020C, 0x02fa027f}, + {0x80210, 0x004a028b}, + {0x80214, 0x020c01df}, + {0x80218, 0x000201e9}, + {0x80200, 0x00013306}, +#else /* panel + CRT */ +#ifdef CONFIG_FO300 + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x301a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0C800C80}, + {0x80014, 0x03200000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00320}, + {0x80024, 0x042a031f}, + {0x80028, 0x0086034a}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201ea}, + {0x80200, 0x00010000}, +#else + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010000}, +#endif /* #ifdef CONFIG_FO300 */ +#endif + {0, 0} +}; +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); +#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300) + } else if (line_number == 2) { +#if defined (CONFIG_STK52XX) + strcpy (info, " on a STK52xx carrier board"); +#endif +#if defined (CONFIG_TB5200) + strcpy (info, " on a TB5200 carrier board"); +#endif +#if defined (CONFIG_FO300) + strcpy (info, " on a FO300 carrier board"); +#endif +#endif + } + else { + info [0] = '\0'; + } +} +#endif + +/* + * Returns SM501 register base address. First thing called in the + * driver. Checks if SM501 is physically present. + */ +unsigned int board_video_init (void) +{ + u16 save, tmp; + int restore, ret; + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller found */ + restore = 0; + ret = 0; + } else { + ret = SM501_MMIO_BASE; + } + + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + return ret; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + return SM501_FB_BASE; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SM501 */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |