diff options
| author | Giuseppe Pagano <giuseppe.pagano@seco.com> | 2013-11-15 16:42:50 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-11-28 07:28:54 (GMT) |
| commit | 953ab736afa0fca087b9e7626daa28ca7adc9fa8 (patch) | |
| tree | 490c68e2756c5e781247693a304db36f206d4234 /board/udoo/clocks.cfg | |
| parent | 8bfa9c692e024bcf2b0b95be33adfa710301f83f (diff) | |
| download | u-boot-953ab736afa0fca087b9e7626daa28ca7adc9fa8.tar.xz | |
udoo: Move and optimize platform register setting.
Previous uDoo configuration adopts register settings for DDR3, clock, muxing,
etc. taken from Nitrogen6x. uDoo schematics is rather different from that board,
and it needs customized setting for most of the registers.
All this changes can be considered atomical since it is part of initial support
of the board.
Patch changes uDoo configuration files path to a specific one, and adopt
optimized value for every configured register.
Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/udoo/clocks.cfg')
| -rw-r--r-- | board/udoo/clocks.cfg | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 0000000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + |