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author | Bartlomiej Sieka <tur@semihalf.com> | 2006-11-01 01:04:38 (GMT) |
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committer | Bartlomiej Sieka <tur@semihalf.com> | 2006-11-01 01:04:38 (GMT) |
commit | 25721b5cec2be4bce79cfade17ec8f6aa1e67526 (patch) | |
tree | c9eb79e6aa910f1a5cfdb7028debcae18a7780c8 /board/v38b/v38b.c | |
parent | ffa150bc90c943ca265170bd1be3f293674dd5c7 (diff) | |
download | u-boot-25721b5cec2be4bce79cfade17ec8f6aa1e67526.tar.xz |
Finish up support for MarelV38B board
- add watchdog support
- enable GPIO_WKUP_7 pin for input
- code cleanup
Diffstat (limited to 'board/v38b/v38b.c')
-rw-r--r-- | board/v38b/v38b.c | 104 |
1 files changed, 56 insertions, 48 deletions
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index 99fe7db..dede996 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -28,43 +28,44 @@ #include <mpc5xxx.h> #include <asm/processor.h> + #ifndef CFG_RAMBOOT static void sdram_start(int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; __asm__ volatile ("sync"); /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); #if SDRAM_DDR /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; __asm__ volatile ("sync"); /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; __asm__ volatile ("sync"); #endif /* SDRAM_DDR */ /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; __asm__ volatile ("sync"); /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; __asm__ volatile ("sync"); /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; __asm__ volatile ("sync"); } #endif /* !CFG_RAMBOOT */ @@ -80,18 +81,18 @@ long int initdram(int board_type) ulong test1, test2; /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ __asm__ volatile ("sync"); /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; __asm__ volatile ("sync"); #if SDRAM_DDR /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; __asm__ volatile ("sync"); #endif /* SDRAM_DDR */ @@ -112,20 +113,20 @@ long int initdram(int board_type) /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -139,22 +140,22 @@ long int initdram(int board_type) /* set SDRAM CS1 size according to the amount of RAM found */ if (dramsize2 > 0) - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); else - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ #else /* CFG_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; if (dramsize >= 0x13) dramsize = (1 << (dramsize - 0x13)) << 20; else dramsize = 0; /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF; if (dramsize2 >= 0x13) dramsize2 = (1 << (dramsize2 - 0x13)) << 20; else @@ -176,7 +177,7 @@ long int initdram(int board_type) if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04; __asm__ volatile ("sync"); } @@ -194,27 +195,42 @@ int checkboard (void) int board_early_init_r(void) { /* - * Now, when we are in RAM, enable flash write access for detection process. - * Note that CS_BOOT cannot be cleared when executing in flash. + * Now, when we are in RAM, enable flash write access for the + * detection process. Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + +#ifdef CONFIG_HW_WATCHDOG + /* + * Enable and configure the direction (output) of PSC3_9 - watchdog + * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's + * Manual. + */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; +#endif /* CONFIG_HW_WATCHDOG */ + + /* + * Enable GPIO_WKUP_7 to "read the status of the actual power + * situation". Default direction is input, so no need to set it + * explicitly. */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7; return 0; } #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset(void) { debug("init_ide_reset\n"); /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } @@ -223,30 +239,22 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ -void led_d4_on(void) -{ - /* TIMER7 as GPIO output low */ - *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; -} - - -void led_d4_off(void) -{ - /* TIMER7 as GPIO output high */ - *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; -} - - +#ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) { -/* TODO fill this in */ + /* + * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog + * we need a positive or negative transition on WDI i.e., our PSC3_9. + */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9; } +#endif /* CONFIG_HW_WATCHDOG */ |