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author | Peter Tyser <ptyser@xes-inc.com> | 2009-05-22 15:26:37 (GMT) |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 22:23:47 (GMT) |
commit | 388517e4b745b00256c2fa201ce7bccb67b4f245 (patch) | |
tree | c2614f3b64c5a881c8640017a0cacc6abee5077b /board/xes/common/fsl_8xxx_clk.c | |
parent | 25623937bb81cae788d767e6c59a11c96fc82866 (diff) | |
download | u-boot-388517e4b745b00256c2fa201ce7bccb67b4f245.tar.xz |
xes: Update Freescale clock code to work with 86xx processors
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/xes/common/fsl_8xxx_clk.c')
-rw-r--r-- | board/xes/common/fsl_8xxx_clk.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c new file mode 100644 index 0000000..0155670 --- /dev/null +++ b/board/xes/common/fsl_8xxx_clk.c @@ -0,0 +1,59 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ +#if defined(CONFIG_MPC85xx) + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#elif defined(CONFIG_MPC86xx) + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; +#endif + u32 gpporcr = gur->gpporcr; + + if (gpporcr & 0x10000) + return 66666666; + else + return 50000000; +} + +#ifdef CONFIG_MPC85xx +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + * Note: 86xx doesn't support asynchronous DDR clk + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + + return 66666666; +} +#endif |