Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

70 files changed, 2640 insertions, 154 deletions

diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
new file mode 100644
index 0000000..4a12c16
--- /dev/null
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1021AIOT
+
+config SYS_BOARD
+	default "ls1021aiot"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021aiot"
+
+endif
diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS
new file mode 100644
index 0000000..2dab798
--- /dev/null
+++ b/board/freescale/ls1021aiot/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1021AIOT BOARD
+M:	Feng Li <feng.li_2@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1021aiot/
+F:	include/configs/ls1021aiot.h
+F:	configs/ls1021aiot_sdcard_defconfig
+F:	configs/ls1021aiot_qspi_defconfig
diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile
new file mode 100644
index 0000000..05709e6
--- /dev/null
+++ b/board/freescale/ls1021aiot/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls1021aiot.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README
new file mode 100644
index 0000000..08b0268
--- /dev/null
+++ b/board/freescale/ls1021aiot/README
@@ -0,0 +1,58 @@
+Overview
+--------
+The LS1021A-IOT is a Freescale reference board that hosts
+the LS1021A SoC.
+
+LS1021AIOT board Overview
+-------------------------
+ - DDR Controller
+	- Supports 1GB un-buffered DDR3L SDRAM discrete
+	devices(32-bit bus) with 4 bit ECC
+	- DDR power supplies 1.35V to all devices with
+	automatic tracking of VTT
+	- Soldered DDR chip
+	- Supprot one fixed speed
+ - Ethernet
+	- Two on-board SGMII 10/100/1G ethernet ports
+	- One Gbit Etherent RGMII interface to 4-ports switch
+	with 4x 10/100/1000 RJ145 ports
+ - CPLD
+	- 8-bit registers in CPLD for system configuration
+	- connected to IFC_AD[0:7]
+ - Power Supplies
+	- 12V@5A DC
+ - SDHC
+	- SDHC port connects directly to a full 8-bit SD/MMC slot
+	- Support for SDIO devices
+ - USB
+	- Two on-board USB 3.0
+	- One on-board USB k22
+ - PCIe
+	- Two MiniPCIe Solts
+ - SATA
+	- Support SATA Connector
+ - AUDIO
+	- AUDIO in and out
+ - I/O Expansion
+	- Arduino Shield Connector
+	- Port0 - CAN/GPIO/Flextimer
+	- Port1 - GPIO/CPLD Expansion
+	- Port2 - SPI/I2C/UART
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address	End Address		Description			Size
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR				240MB
+0x00_4000_0000	0x00_43FF_FFFF	QSPI(Chip select 0)	64MB
+0x00_4400_0000	0x00_47FF_FFFF	QSPI(Chip select 1)	64MB
+0x00_6000_0000	0x00_6000_FFFF	CPLD				64K
+0x00_8000_0000	0x00_BFFF_FFFF	DDR					1GB
+
+Boot description
+-----------------
+LS1021A-IOT support two ways of boot:
+Qspi boot and SD boot
+The board doesn't support boot from another
+source without changing any switch/jumper.
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
new file mode 100644
index 0000000..e27647f
--- /dev/null
+++ b/board/freescale/ls1021aiot/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long long div;
+
+	div = (unsigned long long)(gd->bus_clk / 1000);
+	div *= (unsigned long long)pixclock;
+	do_div(div, 1000000000);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		const char *port,
+		struct fb_videomode *dcu_fb_videomode)
+{
+	const char *name;
+	unsigned int pixel_format;
+
+	if (strncmp(port, "twr_lcd", 4) == 0) {
+		name = "TWR_LCD_RGB card";
+	} else {
+		name = "HDMI";
+		dcu_set_dvi_encoder(dcu_fb_videomode);
+	}
+
+	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+	pixel_format = 32;
+	fsl_dcu_init(xres, yres, pixel_format);
+
+	return 0;
+}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
new file mode 100644
index 0000000..3340e4d
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_sata.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <spl.h>
+
+#include <fsl_validate.h>
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_SIZE		0x40000000
+
+
+int checkboard(void)
+{
+	puts("Board: LS1021AIOT\n");
+
+#ifndef CONFIG_QSPI_BOOT
+	struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 cpldrev;
+
+	cpldrev = in_be32(&dcfg->gpporcr1);
+
+	printf("CPLD:  V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
+		0xf));
+#endif
+	return 0;
+}
+
+void ddrmc_init(void)
+{
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+	out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(500);
+
+	temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	ddrmc_init();
+#endif
+
+	gd->ram_size = DDR_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{CONFIG_SYS_FSL_ESDHC_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+#endif
+
+	arch_soc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+	preloader_console_init();
+
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#endif
+
+	ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+	ls1021a_sata_init();
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
new file mode 100644
index 0000000..b5ac5e2
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
@@ -0,0 +1,14 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..a1984c7
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
@@ -0,0 +1,27 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+
+#Default with 2 x SGMII (no SATA)
+0608000a 00000000 00000000 00000000
+20000000 08407900 60025a00 21046000
+00000000 00000000 00000000 20038000
+20024800 881b1340 00000000 00000000
+
+#SATA set-up
+#0608000a 00000000 00000000 00000000
+#70000000 08007900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#20024800 881b1340 00000000 00000000
+
+#HDMI set-up
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#00000000 881b1340 00000000 00000000
+
+#QE testing
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 00038000
+#20094800 881b1340 00000000 00000000
diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S
new file mode 100644
index 0000000..564145c
--- /dev/null
+++ b/board/freescale/ls1021aiot/psci.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Feng Li <feng.li_2@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+.globl	psci_text_end
+psci_text_end:
+	nop
+	.popsection
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
index 222c71d..d76e913 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 e0106a00 21046000
 00000000 00000000 00000000 00038000
 00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
index 9d99bd8..f0cf9c2 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 60040a00 21046000
 00000000 00000000 00000000 00038000
 00000000 001b7200 00000000 00000000
 
 #disable IFC, enable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
 #60000000 00407900 60040a00 21046000
 #00000000 00000000 00000000 00038000
 #20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
index 2bd398c..10cc4a9 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
 #60000000 00407900 60040a00 21046000
 #00000000 00000000 00000000 00038000
 #00000000 001b7200 00000000 00000000
 
 #disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 60040a00 21046000
 00000000 00000000 00000000 00038000
 20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
index 205606f..f94997d 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 30000000 00007900 60040a00 21046000
 00000000 00000000 00000000 20000000
 00080000 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
index 6767e09..541b604 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 30000000 00007900 60040a00 21046000
 00000000 00000000 00000000 20000000
 20024800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 8c18538..552365b 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void)
 	return 66666666;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk;
+}
+#endif
+
 int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;
@@ -157,6 +164,9 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	u32 usb_pwrfault;
 #endif
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
 
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 	i2c_early_init_f();
@@ -175,6 +185,14 @@ int board_early_init_f(void)
 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
 
+#ifdef CONFIG_LPUART
+	/* We use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[14]);
+	uart &= ~CFG_UART_MUX_MASK;
+	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+	QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index c8dac99..de137ef 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	York Sun <york.sun@nxp.com>
+M:	York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080a/
 F:	include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index d0a88d4..4f9b9c8 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -102,6 +102,11 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -122,7 +127,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	fsl_mc_ldpaa_exit(bd);
 #endif
 
 	return 0;
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 8f78b67..79877d7 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index f288750..2808bd5 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -2,14 +2,14 @@ Overview
 --------
 The LS2080A Development System (QDS) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A
-Layerscape Architecture processor. The LS2080AQDS provides validation and
-SW development platform for the Freescale LS2080A processor series, with
-a complete debugging environment.
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
 
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
 --------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b..59361e9 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -64,7 +64,7 @@ static int sgmii_riser_phy_addr[] = {
 };
 
 /* Slot2 does not have EMI connections */
-#define EMI_NONE	0xFFFFFFFF
+#define EMI_NONE	0xFF
 #define EMI1_SLOT1	0
 #define EMI1_SLOT2	1
 #define EMI1_SLOT3	2
@@ -144,8 +144,10 @@ static void sgmii_configure_repeater(int serdes_port)
 
 		mdelay(10);
 
-		if ((value & 0xfff) == 0x40f) {
+		if ((value & 0xfff) == 0x401) {
 			printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+			miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
+				     0x1f, 0);
 			continue;
 		}
 
@@ -181,28 +183,29 @@ static void sgmii_configure_repeater(int serdes_port)
 				if (ret > 0)
 					goto error;
 
-				mdelay(1);
+				mdelay(100);
 				ret = miiphy_read(dev[mii_bus],
 						  riser_phy_addr[dpmac],
 						  0x11, &value);
 				if (ret > 0)
 					goto error;
-				mdelay(10);
 
-				if ((value & 0xfff) == 0x40f) {
+				if ((value & 0xfff) == 0x401) {
 					printf("DPMAC %d :PHY is configured ",
 					       dpmac_id);
 					printf("after setting repeater 0x%x\n",
 					       value);
 					i = 5;
 					j = 5;
-				} else
+				} else {
 					printf("DPMAC %d :PHY is failed to ",
 					       dpmac_id);
 					printf("configure the repeater 0x%x\n",
 					       value);
 				}
+			}
 		}
+		miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
 	}
 error:
 	if (ret)
@@ -470,7 +473,49 @@ static void initialize_dpmac_to_slot(void)
 		}
 		break;
 
+	case 0x39:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI1_SLOT3;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI1_SLOT3;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
+	case 0x4D:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI_NONE;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
 	case 0x2A:
+	case 0x4B:
+	case 0x4C:
 		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 		       serdes1_prtcl);
 		break;
@@ -505,6 +550,38 @@ static void initialize_dpmac_to_slot(void)
 			lane_to_slot_fsm2[7] = EMI1_SLOT6;
 		}
 		break;
+
+	case 0x47:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		lane_to_slot_fsm2[0] = EMI_NONE;
+		lane_to_slot_fsm2[1] = EMI1_SLOT5;
+		lane_to_slot_fsm2[2] = EMI1_SLOT5;
+		lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[4] = EMI_NONE;
+			lane_to_slot_fsm2[5] = EMI1_SLOT5;
+			lane_to_slot_fsm2[6] = EMI1_SLOT5;
+			lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		}
+		break;
+
+	case 0x57:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[0] = EMI_NONE;
+			lane_to_slot_fsm2[1] = EMI_NONE;
+			lane_to_slot_fsm2[2] = EMI_NONE;
+			lane_to_slot_fsm2[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm2[4] = EMI_NONE;
+		lane_to_slot_fsm2[5] = EMI_NONE;
+		lane_to_slot_fsm2[6] = EMI1_SLOT5;
+		lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		break;
+
 	default:
 		printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 		       __func__ , serdes2_prtcl);
@@ -537,8 +614,10 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 
 	switch (serdes1_prtcl) {
 	case 0x07:
+	case 0x39:
+	case 0x4D:
+		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
 
-		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
 		slot = lane_to_slot_fsm1[lane];
 
 		switch (++slot) {
@@ -559,6 +638,26 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 			wriop_set_mdio(dpmac_id, bus);
 			break;
 		case 3:
+			if (slot == EMI_NONE)
+				return;
+			if (serdes1_prtcl == 0x39) {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 3]);
+			} else {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 3]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
+			bus = mii_dev_for_muxval(EMI1_SLOT3);
+			wriop_set_mdio(dpmac_id, bus);
 			break;
 		case 4:
 			break;
@@ -579,6 +678,8 @@ serdes2:
 	case 0x07:
 	case 0x08:
 	case 0x49:
+	case 0x47:
+	case 0x57:
 		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 							(dpmac_id - 9));
 		slot = lane_to_slot_fsm2[lane];
@@ -597,7 +698,23 @@ serdes2:
 			wriop_set_mdio(dpmac_id, bus);
 		break;
 		case 5:
-		break;
+			if (slot == EMI_NONE)
+				return;
+			if (serdes2_prtcl == 0x47) {
+				wriop_set_phy_address(dpmac_id,
+					      riser_phy_addr[dpmac_id - 10]);
+				if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
+								 env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 11]);
+			} else {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 11]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
+			bus = mii_dev_for_muxval(EMI1_SLOT5);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
 		case 6:
 			/* Slot housing a SGMII riser card? */
 			wriop_set_phy_address(dpmac_id,
@@ -691,6 +808,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 
 	switch (serdes1_prtcl) {
 	case 0x2A:
+	case 0x4B:
+	case 0x4C:
 		/*
 		 * XFI does not need a PHY to work, but to avoid U-Boot use
 		 * default PHY address which is zero to a MAC when it found
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index d07ca18..73a61fd 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -292,14 +292,16 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-#ifdef CONFIG_FSL_MC_ENET
-	int err;
-#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -317,9 +319,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	err = fsl_mc_ldpaa_exit(bd);
-	if (err)
-		return err;
 #endif
 
 	return 0;
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index a20c003..759a146 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080ardb/
 F:	board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index b1613ba..0c9c574 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,13 +1,13 @@
 Overview
 --------
 The LS2080A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2080A
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
 --------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 83d9e7e..02954ef 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -15,6 +15,7 @@
 #include <libfdt.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
+#include <efi_loader.h>
 #include <i2c.h>
 #include <asm/arch/soc.h>
 #include <fsl_sec.h>
@@ -201,6 +202,14 @@ int misc_init_r(void)
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
 
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+		efi_add_memory_map(gd->bd->bi_dram[2].start,
+				   gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
+				   EFI_RESERVED_MEMORY_TYPE, false);
+	}
+#endif
+
 	return 0;
 }
 
@@ -256,14 +265,16 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-#ifdef CONFIG_FSL_MC_ENET
-	int err;
-#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -281,9 +292,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	err = fsl_mc_ldpaa_exit(bd);
-	if (err)
-		return err;
 #endif
 
 	return 0;
diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/chromebook_jerry/Kconfig
deleted file mode 100644
index 3640513..0000000
--- a/board/google/chromebook_jerry/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CHROMEBOOK_JERRY
-
-config SYS_BOARD
-	default "chromebook_jerry"
-
-config SYS_VENDOR
-	default "google"
-
-config SYS_CONFIG_NAME
-	default "chromebook_jerry"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/google/chromebook_jerry/MAINTAINERS b/board/google/chromebook_jerry/MAINTAINERS
deleted file mode 100644
index b01b6cd..0000000
--- a/board/google/chromebook_jerry/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CHROMEBOOK JERRY BOARD
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-F:	board/google/chromebook_jerry/
-F:	include/configs/chromebook_jerry.h
-F:	configs/chromebook_jerry_defconfig
diff --git a/board/google/chromebook_jerry/jerry.c b/board/google/chromebook_jerry/jerry.c
deleted file mode 100644
index 5119e95..0000000
--- a/board/google/chromebook_jerry/jerry.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
new file mode 100644
index 0000000..770e9aa
--- /dev/null
+++ b/board/google/veyron/Kconfig
@@ -0,0 +1,47 @@
+if TARGET_CHROMEBOOK_JERRY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBIT_MICKEY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBOOK_MINNIE
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS
new file mode 100644
index 0000000..d582cb0
--- /dev/null
+++ b/board/google/veyron/MAINTAINERS
@@ -0,0 +1,20 @@
+CHROMEBOOK JERRY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_jerry_defconfig
+
+CHROMEBIT MICKEY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebit_mickey_defconfig
+
+CHROMEBIT MINNIE BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebit_minnie_defconfig
diff --git a/board/google/chromebook_jerry/Makefile b/board/google/veyron/Makefile
index d29a063..9868357 100644
--- a/board/google/chromebook_jerry/Makefile
+++ b/board/google/veyron/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y	+= jerry.o
+obj-y	+= veyron.o
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
new file mode 100644
index 0000000..20297e1
--- /dev/null
+++ b/board/google/veyron/veyron.c
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * We should increase the DDR voltage to 1.2V using the PWM regulator.
+ * There is a U-Boot driver for this but it may need to add support for the
+ * 'voltage-table' property.
+ */
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
index 4ce2c98..dcb25ac 100644
--- a/board/raspberrypi/rpi/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= rpi.o
+obj-y	+= lowlevel_init.o
diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S
new file mode 100644
index 0000000..cdbd8e1
--- /dev/null
+++ b/board/raspberrypi/rpi/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global fw_dtb_pointer
+fw_dtb_pointer:
+#ifdef CONFIG_ARM64
+	.dword 0x0
+#else
+	.word 0x0
+#endif
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+#ifdef CONFIG_ARM64
+	adr	x8, fw_dtb_pointer
+	str	x0, [x8]
+#else
+	str	r2, fw_dtb_pointer
+#endif
+
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 6245b36..ffd6d31 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -25,6 +25,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* From lowlevel_init.S */
+extern unsigned long fw_dtb_pointer;
+
 static const struct bcm2835_gpio_platdata gpio_platdata = {
 	.base = BCM2835_GPIO_BASE,
 };
@@ -285,6 +288,31 @@ static void set_fdtfile(void)
 	setenv("fdtfile", fdtfile);
 }
 
+/*
+ * If the firmware provided a valid FDT at boot time, let's expose it in
+ * ${fdt_addr} so it may be passed unmodified to the kernel.
+ */
+static void set_fdt_addr(void)
+{
+	if (getenv("fdt_addr"))
+		return;
+
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return;
+
+	setenv_hex("fdt_addr", fw_dtb_pointer);
+}
+
+/*
+ * Prevent relocation from stomping on a firmware provided FDT blob.
+ */
+unsigned long board_get_usable_ram_top(unsigned long total_size)
+{
+	if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
+		return gd->ram_top;
+	return fw_dtb_pointer & ~0xffff;
+}
+
 static void set_usbethaddr(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
@@ -356,6 +384,7 @@ static void set_serial_number(void)
 
 int misc_init_r(void)
 {
+	set_fdt_addr();
 	set_fdtfile();
 	set_usbethaddr();
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index c6e6cd3..c437f1b 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -71,5 +71,5 @@ void dram_init_banksize(void)
 {
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = 0x80000000;
+	gd->bd->bi_dram[0].size = 0x7e000000;
 }
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index d7dc55b..e23d45e 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -232,6 +232,11 @@ M:	Jelle van der Waa <jelle@vdwaa.nl>
 S:	Maintained
 F:	configs/nanopi_neo_defconfig
 
+NINTENDO NES CLASSIC EDITION BOARD
+M:	FUKAUMI Naoki <naobsd@gmail.com>
+S:	Maintained
+F:	configs/Nintendo_NES_Classic_Edition_defconfig
+
 R16 EVB PARROT BOARD
 M:	Quentin Schulz <quentin.schulz@free-electrons.com>
 S:	Maintained
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index fc1353a..da9eab4 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -64,10 +64,16 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /*
  * Read header information from EEPROM into global structure.
  */
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
 {
-	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+		printf("ti_i2c_eeprom_init failed\n");
 }
+#endif
 
 #ifndef CONFIG_DM_SERIAL
 struct serial_device *default_serial_console(void)
@@ -248,9 +254,6 @@ void am33xx_spl_board_init(void)
 {
 	int mpu_vdd;
 
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 
@@ -388,11 +391,6 @@ void am33xx_spl_board_init(void)
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_evm_sk())
 		return &dpll_ddr_evm_sk;
 	else if (board_is_bone_lt() || board_is_icev2())
@@ -422,9 +420,6 @@ void set_uart_mux_conf(void)
 
 void set_mux_conf_regs(void)
 {
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	enable_board_pin_mux();
 }
 
@@ -462,9 +457,6 @@ const struct ctrl_ioregs ioregs = {
 
 void sdram_init(void)
 {
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_evm_sk()) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@@ -642,13 +634,8 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	int rc;
 	char *name = NULL;
 
-	rc = read_eeprom();
-	if (rc)
-		puts("Could not get board ID.\n");
-
 	if (board_is_bbg1())
 		name = "BBG1";
 	set_board_info_env(name);
@@ -779,9 +766,6 @@ int board_eth_init(bd_t *bis)
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 
 #ifdef CONFIG_DRIVER_TI_CPSW
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_bone() || board_is_bone_lt() ||
 	    board_is_idk()) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f04a06e..ba6f88f 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -39,10 +39,13 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /*
  * Read header information from EEPROM into global structure.
  */
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
 {
-	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+	if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+		printf("ti_i2c_eeprom_init failed\n");
 }
+#endif
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -337,9 +340,6 @@ const struct dpll_params *get_dpll_ddr_params(void)
 {
 	int ind = get_sys_clk_index();
 
-	if (read_eeprom() < 0)
-		return NULL;
-
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
 	else if (board_is_evm() || board_is_sk())
@@ -495,9 +495,6 @@ void scale_vcores(void)
 {
 	const struct dpll_params *mpu_params;
 
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	/* Ensure I2C is initialized for PMIC configuration */
 	gpi2c_init();
 
@@ -537,8 +534,6 @@ static void enable_vtt_regulator(void)
 
 void sdram_init(void)
 {
-	if (read_eeprom() < 0)
-		return;
 	/*
 	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 	 * GP EMV has 1GB DDR3 connected to EMIF
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 64de602..f3e3f0b 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -447,26 +447,6 @@ int spl_start_uboot(void)
 #endif
 
 #ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS1_BASE,
-	.tx_fifo_resize = false,
-	.index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
-	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
-	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
-	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
-	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
-	.index = 0,
-};
-
 static struct dwc3_device usb_otg_ss2 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = DRA7_USB_OTG_SS2_BASE,
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 7ef2d2b..879f8b5 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -6,12 +6,12 @@
 #
 
 obj-y += board.o
-obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
-obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
-obj-$(CONFIG_K2E_EVM) += board_k2e.o
-obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
-obj-$(CONFIG_K2L_EVM) += board_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
-obj-$(CONFIG_K2G_EVM) += board_k2g.o
-obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o
+obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o
+obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o
diff --git a/board/topic/zynq/MAINTAINERS b/board/topic/zynq/MAINTAINERS
new file mode 100644
index 0000000..d795b30
--- /dev/null
+++ b/board/topic/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+TOPIC BOARD
+M:	Mike Looijmans <mike.looijmans@topic.nl>
+S:	Maintained
+F:	board/topic/zynq/
+F:	include/configs/topic*.h
+F:	configs/topic_*_defconfig
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
new file mode 100644
index 0000000..eaf59cd
--- /dev/null
+++ b/board/topic/zynq/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
+
+# Remove quotes
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c
new file mode 100644
index 0000000..a95c9d1
--- /dev/null
+++ b/board/topic/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c
new file mode 100644
index 0000000..b1d45c2
--- /dev/null
+++ b/board/topic/zynq/ps7_init_common.c
@@ -0,0 +1,117 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+#include <asm/io.h>
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+#define APU_FREQ  666666666
+
+#define PS7_MASK_POLL_TIME 100000000
+
+/* IO accessors. No memory barriers desired. */
+static inline void iowrite(unsigned long val, unsigned long addr)
+{
+	__raw_writel(val, addr);
+}
+
+static inline unsigned long ioread(unsigned long addr)
+{
+	return __raw_readl(addr);
+}
+
+/* start timer */
+static void perf_start_clock(void)
+{
+	iowrite((1 << 0) | /* Timer Enable */
+		(1 << 3) | /* Auto-increment */
+		(0 << 8), /* Pre-scale */
+		SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* Compute mask for given delay in miliseconds*/
+static int get_number_of_cycles_for_delay(unsigned int delay)
+{
+	return (APU_FREQ / (2 * 1000)) * delay;
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+	iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
+	iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
+}
+
+static void perf_reset_and_start_timer(void)
+{
+	perf_reset_clock();
+	perf_start_clock();
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+	unsigned long *ptr = ps7_config_init;
+	unsigned long opcode;
+	unsigned long addr;
+	unsigned long val;
+	unsigned long mask;
+	unsigned int numargs;
+	int i;
+	int delay;
+
+	for (;;) {
+		opcode = ptr[0];
+		if (opcode == OPCODE_EXIT)
+			return PS7_INIT_SUCCESS;
+		addr = (opcode & OPCODE_ADDRESS_MASK);
+
+		switch (opcode & ~OPCODE_ADDRESS_MASK) {
+		case OPCODE_MASKWRITE:
+			numargs = 3;
+			mask = ptr[1];
+			val = ptr[2];
+			iowrite((ioread(addr) & ~mask) | (val & mask), addr);
+			break;
+
+		case OPCODE_MASKPOLL:
+			numargs = 2;
+			mask = ptr[1];
+			i = 0;
+			while (!(ioread(addr) & mask)) {
+				if (i == PS7_MASK_POLL_TIME)
+					return PS7_INIT_TIMEOUT;
+				i++;
+			}
+			break;
+
+		case OPCODE_MASKDELAY:
+			numargs = 2;
+			mask = ptr[1];
+			delay = get_number_of_cycles_for_delay(mask);
+			perf_reset_and_start_timer();
+			while (ioread(addr) < delay)
+				;
+			break;
+
+		default:
+			return PS7_INIT_CORRUPT;
+		}
+
+		ptr += numargs;
+	}
+}
diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h
new file mode 100644
index 0000000..ef719ac
--- /dev/null
+++ b/board/topic/zynq/ps7_init_gpl.h
@@ -0,0 +1,34 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define OPCODE_EXIT       0U
+#define OPCODE_MASKWRITE  0U
+#define OPCODE_MASKPOLL   1U
+#define OPCODE_MASKDELAY  2U
+#define OPCODE_ADDRESS_MASK (~3U)
+
+/* Sentinel */
+#define EMIT_EXIT()                     OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)       OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask)      OPCODE_MASKDELAY | addr, mask
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS   (0)
+#define PS7_INIT_CORRUPT   (1)
+#define PS7_INIT_TIMEOUT   (2)
+#define PS7_POLL_FAILED_DDR_INIT (3)
+#define PS7_POLL_FAILED_DMA      (4)
+#define PS7_POLL_FAILED_PLL      (5)
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
new file mode 100644
index 0000000..b195d7a
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -0,0 +1,227 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_regs.txt b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
new file mode 100644
index 0000000..2ad9da6
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x1210     // MIO configuration
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x210
+0xf8000720 0x202
+0xf8000724 0x1210
+0xf8000728 0x1210
+0xf800072c 0x1210
+0xf8000730 0x1210
+0xf8000734 0x1210
+0xf8000738 0x1211
+0xf800073c 0x1200
+0xf8000740 0x1210
+0xf8000744 0x1210
+0xf8000748 0x1210
+0xf800074c 0x1210
+0xf8000750 0x1210
+0xf8000754 0x1210
+0xf8000758 0x1210
+0xf800075c 0x1210
+0xf8000760 0x1201
+0xf8000764 0x200
+0xf8000768 0x12e1
+0xf800076c 0x2e0
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1261
+0xf80007bc 0x1260
+0xf80007c0 0x1261
+0xf80007c4 0x1261
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1240
+0xf80007d4 0x1240
+0xf8000830 0x180037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
new file mode 100644
index 0000000..5a92336
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -0,0 +1,233 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
new file mode 100644
index 0000000..7b102de
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
+0xf8000700 0x1202     // MIO configuration
+0xf8000704 0x1202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1202
+0xf8000744 0x1202
+0xf8000748 0x1202
+0xf800074c 0x1202
+0xf8000750 0x1202
+0xf8000754 0x1202
+0xf8000758 0x1203
+0xf800075c 0x1203
+0xf8000760 0x1203
+0xf8000764 0x203
+0xf8000768 0x1203
+0xf800076c 0x203
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1201
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1280
+0xf80007d4 0x1280
+0xf8000830 0x2f0037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index f1dcda5..16224da 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -9,4 +9,22 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "apalis_t30"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index 3f56971..3d83491 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014
+ *  (C) Copyright 2014-2016
  *  Marcel Ziswiler <marcel@ziswiler.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -17,6 +17,8 @@
 
 #include "pinmux-config-apalis_t30.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PMU_I2C_ADDRESS		0x2D
 #define MAX_I2C_RETRY		3
 
@@ -29,6 +31,14 @@ int arch_misc_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	printf("Model: Toradex Apalis T30 %dGB\n",
+	       (gd->ram_size == 0x40000000) ? 1 : 2);
+
+	return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig
index 7bba26b..414a600 100644
--- a/board/toradex/colibri_imx7/Kconfig
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -16,5 +16,21 @@ config COLIBRI_IMX7_EXT_PHYCLK
 	  clock source.
 	default y
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_OFFSET2
+	default "133120"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
 
 endif
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
index 949407a..f646baa 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -9,4 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_pxa270"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "262144"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 3def0a6..932b900 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -2,16 +2,20 @@
  * Toradex Colibri PXA270 Support
  *
  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
 #include <asm/arch/pxa.h>
-#include <netdev.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/regs-uart.h>
 #include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pxa.h>
+#include <netdev.h>
 #include <serial.h>
 #include <usb.h>
 
@@ -32,6 +36,13 @@ int board_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri PXA270\n");
+
+	return 0;
+}
+
 int dram_init(void)
 {
 	pxa2xx_dram_init();
@@ -105,3 +116,14 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+static const struct pxa_serial_platdata serial_platdata = {
+	.base = (struct pxa_uart_regs *)FFUART_BASE,
+	.port = FFUART_INDEX,
+	.baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(pxa_serials) = {
+	.name = "serial_pxa",
+	.platdata = &serial_platdata,
+};
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
index 7f373b2..a43acdd 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -9,4 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_t20"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "3145728"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 68fbf49..01b55be 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -14,6 +14,9 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define PMU_I2C_ADDRESS		0x34
 #define MAX_I2C_RETRY		3
@@ -61,6 +64,16 @@ int arch_misc_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri T20 %dMB V%s\n",
+	       (gd->ram_size == 0x10000000) ? 256 : 512,
+	       (nand_info[0]->erasesize >> 10 == 512) ?
+	       ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
+
+	return 0;
+}
+
 #ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
index 3e436a2..68ef82b 100644
--- a/board/toradex/colibri_t30/Kconfig
+++ b/board/toradex/colibri_t30/Kconfig
@@ -9,4 +9,22 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_t30"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index e32362a..707d07e 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014
+ *  (C) Copyright 2014-2016
  *  Stefan Agner <stefan@agner.ch>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -24,6 +24,13 @@ int arch_misc_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri T30 1GB\n");
+
+	return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
index 2c3cb30..bf9bb01 100644
--- a/board/toradex/colibri_vf/Kconfig
+++ b/board/toradex/colibri_vf/Kconfig
@@ -15,4 +15,18 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "colibri_vf"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index c65ccb3..e65d9c3 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -528,22 +528,6 @@ int checkboard(void)
 	return 0;
 }
 
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
-{
-	unsigned short usb_pid;
-
-	put_unaligned(CONFIG_TRDX_VID, &dev->idVendor);
-
-	if (is_colibri_vf61())
-		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
-	else
-		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
-
-	put_unaligned(usb_pid, &dev->idProduct);
-
-	return 0;
-}
-
 #ifdef CONFIG_USB_EHCI_VF
 int board_ehci_hcd_init(int port)
 {
diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig
new file mode 100644
index 0000000..b33baef
--- /dev/null
+++ b/board/toradex/common/Kconfig
@@ -0,0 +1,69 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:	GPL-2.0+
+
+menuconfig TDX_CFG_BLOCK
+	bool "Enable Toradex config block support"
+	select OF_BOARD_SETUP
+	help
+	  The Toradex config block stored production data on the on-module
+	  flash device (NAND, NOR or eMMC). The area is normally preserved by
+	  software and contains the serial number (out of which the MAC
+	  address is generated) and the exact module type.
+
+# Helper config to determine the correct default location of the cfg block
+config TDX_HAVE_MMC
+	bool
+
+config TDX_HAVE_NAND
+	bool
+
+config TDX_HAVE_NOR
+	bool
+
+if TDX_CFG_BLOCK
+
+config TDX_CFG_BLOCK_IS_IN_MMC
+	bool
+	depends on TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NAND
+	bool
+	depends on TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NOR
+	bool
+	depends on TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	int "Toradex config block eMMC device ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_PART
+	int "Toradex config block eMMC partition ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_OFFSET
+	int "Toradex config block offset"
+	help
+	  Specify the byte offset of the Toradex config block within the flash
+	  device the config block is stored on.
+
+config TDX_CFG_BLOCK_OFFSET2
+	int "Toradex config block offset, second instance"
+	default 0
+	help
+	  Specify the byte offset of the 2nd instance of the Toradex config block
+	  within the flash device the config block is stored on.
+	  Set to 0 on modules which have no 2nd instance.
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	bool "Set the second Ethernet address"
+	help
+	  For each serial number two Ethernet addresses are available for dual
+	  Ethernet carrier boards. This options enables the code to set the
+	  second Ethernet address as environment variable (eth1addr).
+
+endif
diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile
new file mode 100644
index 0000000..d645f5a
--- /dev/null
+++ b/board/toradex/common/Makefile
@@ -0,0 +1,11 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:	GPL-2.0+
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
+obj-y += tdx-common.o
+endif
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
new file mode 100644
index 0000000..0014ce8
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "tdx-cfg-block.h"
+
+#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
+#include <asm/arch/sys_proto.h>
+#else
+#define is_cpu_type(cpu) (0)
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+#include <asm/arch-pxa/pxa.h>
+#else
+#define cpu_is_pxa27x(cpu) (0)
+#endif
+#include <cli.h>
+#include <console.h>
+#include <flash.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TAG_VALID	0xcf01
+#define TAG_MAC		0x0000
+#define TAG_HW		0x0008
+#define TAG_INVALID	0xffff
+
+#define TAG_FLAG_VALID	0x1
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+#define TDX_CFG_BLOCK_MAX_SIZE 512
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#else
+#error Toradex config block location not set
+#endif
+
+struct toradex_tag {
+	u32 len:14;
+	u32 flags:2;
+	u32 id:16;
+};
+
+bool valid_cfgblock;
+struct toradex_hw tdx_hw_tag;
+struct toradex_eth_addr tdx_eth_addr;
+u32 tdx_serial;
+
+const char * const toradex_modules[] = {
+	 [0] = "UNKNOWN MODULE",
+	 [1] = "Colibri PXA270 312MHz",
+	 [2] = "Colibri PXA270 520MHz",
+	 [3] = "Colibri PXA320 806MHz",
+	 [4] = "Colibri PXA300 208MHz",
+	 [5] = "Colibri PXA310 624MHz",
+	 [6] = "Colibri PXA320 806MHz IT",
+	 [7] = "Colibri PXA300 208MHz XT",
+	 [8] = "Colibri PXA270 312MHz",
+	 [9] = "Colibri PXA270 520MHz",
+	[10] = "Colibri VF50 128MB", /* not currently on sale */
+	[11] = "Colibri VF61 256MB",
+	[12] = "Colibri VF61 256MB IT",
+	[13] = "Colibri VF50 128MB IT",
+	[14] = "Colibri iMX6 Solo 256MB",
+	[15] = "Colibri iMX6 DualLite 512MB",
+	[16] = "Colibri iMX6 Solo 256MB IT",
+	[17] = "Colibri iMX6 DualLite 512MB IT",
+	[18] = "UNKNOWN MODULE",
+	[19] = "UNKNOWN MODULE",
+	[20] = "Colibri T20 256MB",
+	[21] = "Colibri T20 512MB",
+	[22] = "Colibri T20 512MB IT",
+	[23] = "Colibri T30 1GB",
+	[24] = "Colibri T20 256MB IT",
+	[25] = "Apalis T30 2GB",
+	[26] = "Apalis T30 1GB",
+	[27] = "Apalis iMX6 Quad 1GB",
+	[28] = "Apalis iMX6 Quad 2GB IT",
+	[29] = "Apalis iMX6 Dual 512MB",
+	[30] = "Colibri T30 1GB IT",
+	[31] = "Apalis T30 1GB IT",
+	[32] = "Colibri iMX7 Solo 256MB",
+	[33] = "Colibri iMX7 Dual 512MB",
+	[34] = "Apalis TK1 2GB",
+	[35] = "Apalis iMX6 Dual 1GB IT",
+};
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
+static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
+{
+	struct mmc *mmc;
+	int dev = CONFIG_TDX_CFG_BLOCK_DEV;
+	int offset = CONFIG_TDX_CFG_BLOCK_OFFSET;
+	uint part = CONFIG_TDX_CFG_BLOCK_PART;
+	uint blk_start;
+	int ret = 0;
+
+	/* Read production parameter config block from eMMC */
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		puts("No MMC card found\n");
+		ret = -ENODEV;
+		goto out;
+	}
+	if (part != mmc->block_dev.hwpart) {
+		if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
+			puts("MMC partition switch failed\n");
+			ret = -ENODEV;
+			goto out;
+		}
+	}
+	if (offset < 0)
+		offset += mmc->capacity;
+	blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+
+	if (!write) {
+		/* Careful reads a whole block of 512 bytes into config_block */
+		if (blk_dread(mmc_get_blk_desc(mmc), blk_start, 1,
+			      (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+		/* Flush cache after read */
+		flush_cache((ulong)(unsigned char *)config_block, 512);
+	} else {
+		/* Just writing one 512 byte block */
+		if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
+			       (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+	}
+
+out:
+	/* Switch back to regular eMMC user partition */
+	blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NAND
+static int read_tdx_cfg_block_from_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+	/* Read production parameter config block from NAND page */
+	return nand_read_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
+			 &size, NULL, TDX_CFG_BLOCK_MAX_SIZE, config_block);
+}
+
+static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+	/* Write production parameter config block to NAND page */
+	return nand_write_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
+				   &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+				   config_block, WITH_WR_VERIFY);
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
+static int read_tdx_cfg_block_from_nor(unsigned char *config_block)
+{
+	/* Read production parameter config block from NOR flash */
+	memcpy(config_block, (void *)CONFIG_TDX_CFG_BLOCK_OFFSET,
+	       TDX_CFG_BLOCK_MAX_SIZE);
+	return 0;
+}
+
+static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
+{
+	/* Write production parameter config block to NOR flash */
+	return flash_write((void *)config_block, CONFIG_TDX_CFG_BLOCK_OFFSET,
+			   TDX_CFG_BLOCK_MAX_SIZE);
+}
+#endif
+
+int read_tdx_cfg_block(void)
+{
+	int ret = 0;
+	u8 *config_block = NULL;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return -ENOMEM;
+	}
+
+	memset(config_block, 0, size);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	ret = tdx_cfg_block_mmc_storage(config_block, 0);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	ret = read_tdx_cfg_block_from_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	ret = read_tdx_cfg_block_from_nor(config_block);
+#else
+	ret = -EINVAL;
+#endif
+	if (ret)
+		goto out;
+
+	/* Expect a valid tag first */
+	tag = (struct toradex_tag *)config_block;
+	if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
+		valid_cfgblock = false;
+		ret = -EINVAL;
+		goto out;
+	}
+	valid_cfgblock = true;
+	offset = 4;
+
+	while (offset < TDX_CFG_BLOCK_MAX_SIZE) {
+		tag = (struct toradex_tag *)(config_block + offset);
+		offset += 4;
+		if (tag->id == TAG_INVALID)
+			break;
+
+		if (tag->flags == TAG_FLAG_VALID) {
+			switch (tag->id) {
+			case TAG_MAC:
+				memcpy(&tdx_eth_addr, config_block + offset,
+				       6);
+
+				/* NIC part of MAC address is serial number */
+				tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
+				break;
+			case TAG_HW:
+				memcpy(&tdx_hw_tag, config_block + offset, 8);
+				break;
+			}
+		}
+
+		/* Get to next tag according to current tags length */
+		offset += tag->len * 4;
+	}
+
+	/* Cap product id to avoid issues with a yet unknown one */
+	if (tdx_hw_tag.prodid > (sizeof(toradex_modules) /
+				  sizeof(toradex_modules[0])))
+		tdx_hw_tag.prodid = 0;
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int get_cfgblock_interactive(void)
+{
+	char message[CONFIG_SYS_CBSIZE];
+	char *soc;
+	char it = 'n';
+	int len;
+
+	if (cpu_is_pxa27x())
+		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
+	else
+		sprintf(message, "Is the module an IT version? [y/N] ");
+
+	len = cli_readline(message);
+	it = console_buffer[0];
+
+	soc = getenv("soc");
+	if (!strcmp("mx6", soc)) {
+#ifdef CONFIG_MACH_TYPE
+		if (it == 'y' || it == 'Y')
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D_IT;
+		else
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D;
+#else
+		if (it == 'y' || it == 'Y')
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
+		else
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6S;
+#endif /* CONFIG_MACH_TYPE */
+	} else if (!strcmp("imx7d", soc)) {
+		tdx_hw_tag.prodid = COLIBRI_IMX7D;
+	} else if (!strcmp("imx7s", soc)) {
+		tdx_hw_tag.prodid = COLIBRI_IMX7S;
+	} else if (!strcmp("tegra20", soc)) {
+		if (it == 'y' || it == 'Y')
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT;
+		else
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB;
+	} else if (cpu_is_pxa27x()) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
+		else
+			tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+#ifdef CONFIG_MACH_TYPE
+	} else if (!strcmp("tegra30", soc)) {
+		if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = APALIS_T30_IT;
+			else
+				if (gd->ram_size == 0x40000000)
+					tdx_hw_tag.prodid = APALIS_T30_1GB;
+				else
+					tdx_hw_tag.prodid = APALIS_T30_2GB;
+		} else {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_T30_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T30;
+		}
+#endif /* CONFIG_MACH_TYPE */
+	} else if (!strcmp("tegra124", soc)) {
+		tdx_hw_tag.prodid = APALIS_TK1_2GB;
+	} else if (!strcmp("vf500", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF50_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF50;
+	} else if (!strcmp("vf610", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF61_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF61;
+	} else {
+		printf("Module type not detectable due to unknown SoC\n");
+		return -1;
+	}
+
+	while (len < 4) {
+		sprintf(message, "Enter the module version (e.g. V1.1B): V");
+		len = cli_readline(message);
+	}
+
+	tdx_hw_tag.ver_major = console_buffer[0] - '0';
+	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
+	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+		tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
+				       COLIBRI_PXA270_V1_312MHZ);
+
+	while (len < 8) {
+		sprintf(message, "Enter module serial number: ");
+		len = cli_readline(message);
+	}
+
+	tdx_serial = simple_strtoul(console_buffer, NULL, 10);
+
+	return 0;
+}
+
+static int get_cfgblock_barcode(char *barcode)
+{
+	if (strlen(barcode) < 16) {
+		printf("Argument too short, barcode is 16 chars long\n");
+		return -1;
+	}
+
+	/* Get hardware information from the first 8 digits */
+	tdx_hw_tag.ver_major = barcode[4] - '0';
+	tdx_hw_tag.ver_minor = barcode[5] - '0';
+	tdx_hw_tag.ver_assembly = barcode[7] - '0';
+
+	barcode[4] = '\0';
+	tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10);
+
+	/* Parse second part of the barcode (serial number */
+	barcode += 8;
+	tdx_serial = simple_strtoul(barcode, NULL, 10);
+
+	return 0;
+}
+
+static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	u8 *config_block;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset = 0;
+	int ret = CMD_RET_SUCCESS;
+	int err;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	memset(config_block, 0xff, size);
+
+	read_tdx_cfg_block();
+	if (valid_cfgblock) {
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+		/*
+		 * On NAND devices, recreation is only allowed if the page is
+		 * empty (config block invalid...)
+		 */
+		printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET / nand_info[0]->erasesize);
+		goto out;
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+		/*
+		 * On NOR devices, recreation is only allowed if the sector is
+		 * empty and write protection is off (config block invalid...)
+		 */
+		printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET);
+		goto out;
+#else
+		char message[CONFIG_SYS_CBSIZE];
+		sprintf(message,
+			"A valid Toradex config block is present, still recreate? [y/N] ");
+
+		if (!cli_readline(message))
+			goto out;
+
+		if (console_buffer[0] != 'y' && console_buffer[0] != 'Y')
+			goto out;
+#endif
+	}
+
+	/* Parse new Toradex config block data... */
+	if (argc < 3)
+		err = get_cfgblock_interactive();
+	else
+		err = get_cfgblock_barcode(argv[2]);
+
+	if (err) {
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	/* Convert serial number to MAC address (the storage format) */
+	tdx_eth_addr.oui = htonl(0x00142dUL << 8);
+	tdx_eth_addr.nic = htonl(tdx_serial << 8);
+
+	/* Valid Tag */
+	tag = (struct toradex_tag *)config_block;
+	tag->id = TAG_VALID;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 0;
+	offset += 4;
+
+	/* Product Tag */
+	tag = (struct toradex_tag *)(config_block + offset);
+	tag->id = TAG_HW;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 2;
+	offset += 4;
+
+	memcpy(config_block + offset, &tdx_hw_tag, 8);
+	offset += 8;
+
+	/* MAC Tag */
+	tag = (struct toradex_tag *)(config_block + offset);
+	tag->id = TAG_MAC;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 2;
+	offset += 4;
+
+	memcpy(config_block + offset, &tdx_eth_addr, 6);
+	offset += 6;
+	memset(config_block + offset, 0, 32 - offset);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	err = tdx_cfg_block_mmc_storage(config_block, 1);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	err = write_tdx_cfg_block_to_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	err = write_tdx_cfg_block_to_nor(config_block);
+#else
+	err = -EINVAL;
+#endif
+	if (err) {
+		printf("Failed to write Toradex config block: %d\n", ret);
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	printf("Toradex config block successfully written\n");
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[1], "create")) {
+		return do_cfgblock_create(cmdtp, flag, argc, argv);
+	} else if (!strcmp(argv[1], "reload")) {
+		ret = read_tdx_cfg_block();
+		if (ret) {
+			printf("Failed to reload Toradex config block: %d\n",
+			       ret);
+			return CMD_RET_FAILURE;
+		}
+		return CMD_RET_SUCCESS;
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	cfgblock, 3, 0, do_cfgblock,
+	"Toradex config block handling commands",
+	"create [barcode] - (Re-)create Toradex config block\n"
+	"cfgblock reload - Reload Toradex config block from flash"
+);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
new file mode 100644
index 0000000..fd7c362
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TDX_CFG_BLOCK_H
+#define _TDX_CFG_BLOCK_H
+
+#include "tdx-common.h"
+
+struct toradex_hw {
+	u16 ver_major;
+	u16 ver_minor;
+	u16 ver_assembly;
+	u16 prodid;
+};
+
+struct toradex_eth_addr {
+	u32 oui:24;
+	u32 nic:24;
+} __attribute__((__packed__));
+
+enum {
+	COLIBRI_PXA270_V1_312MHZ = 1,
+	COLIBRI_PXA270_V1_520MHZ,
+	COLIBRI_PXA320,
+	COLIBRI_PXA300,
+	COLIBRI_PXA310,
+	COLIBRI_PXA320_IT,
+	COLIBRI_PXA300_XT,
+	COLIBRI_PXA270_312MHZ,
+	COLIBRI_PXA270_520MHZ,
+	COLIBRI_VF50, /* not currently on sale */
+	COLIBRI_VF61,
+	COLIBRI_VF61_IT,
+	COLIBRI_VF50_IT,
+	COLIBRI_IMX6S,
+	COLIBRI_IMX6DL,
+	COLIBRI_IMX6S_IT,
+	COLIBRI_IMX6DL_IT,
+	COLIBRI_T20_256MB = 20,
+	COLIBRI_T20_512MB,
+	COLIBRI_T20_512MB_IT,
+	COLIBRI_T30,
+	COLIBRI_T20_256MB_IT,
+	APALIS_T30_2GB,
+	APALIS_T30_1GB,
+	APALIS_IMX6Q,
+	APALIS_IMX6Q_IT,
+	APALIS_IMX6D,
+	COLIBRI_T30_IT,
+	APALIS_T30_IT,
+	COLIBRI_IMX7S,
+	COLIBRI_IMX7D,
+	APALIS_TK1_2GB,
+	APALIS_IMX6D_IT,
+};
+
+extern const char * const toradex_modules[];
+extern bool valid_cfgblock;
+extern struct toradex_hw tdx_hw_tag;
+extern struct toradex_eth_addr tdx_eth_addr;
+extern u32 tdx_serial;
+
+int read_tdx_cfg_block(void);
+
+#endif /* _TDX_CFG_BLOCK_H */
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
new file mode 100644
index 0000000..f1ab794
--- /dev/null
+++ b/board/toradex/common/tdx-common.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <g_dnl.h>
+#include <libfdt.h>
+
+#include "tdx-cfg-block.h"
+#include "tdx-common.h"
+
+#ifdef CONFIG_TDX_CFG_BLOCK
+static char tdx_serial_str[9];
+static char tdx_board_rev_str[6];
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	/* Check validity */
+	if (!tdx_hw_tag.ver_major)
+		return 0;
+
+	return ((tdx_hw_tag.ver_major & 0xff) << 8) |
+		((tdx_hw_tag.ver_minor & 0xf) << 4) |
+		((tdx_hw_tag.ver_assembly & 0xf) + 0xa);
+}
+#endif /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	int array[8];
+	unsigned int serial = tdx_serial;
+	int i;
+
+	serialnr->low = 0;
+	serialnr->high = 0;
+
+	/* Check validity */
+	if (serial) {
+		/*
+		 * Convert to Linux serial number format (hexadecimal coded
+		 * decimal)
+		 */
+		i = 7;
+		while (serial) {
+			array[i--] = serial % 10;
+			serial /= 10;
+		}
+		while (i >= 0)
+			array[i--] = 0;
+		serial = array[0];
+		for (i = 1; i < 8; i++) {
+			serial *= 16;
+			serial += array[i];
+		}
+
+		serialnr->low = serial;
+	}
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int show_board_info(void)
+{
+	unsigned char ethaddr[6];
+
+	if (read_tdx_cfg_block()) {
+		printf("Missing Toradex config block\n");
+		checkboard();
+		return 0;
+	}
+
+	/* board serial-number */
+	sprintf(tdx_serial_str, "%08u", tdx_serial);
+	sprintf(tdx_board_rev_str, "V%1d.%1d%c",
+		tdx_hw_tag.ver_major,
+		tdx_hw_tag.ver_minor,
+		(char)tdx_hw_tag.ver_assembly + 'A');
+
+	setenv("serial#", tdx_serial_str);
+
+	/*
+	 * Check if environment contains a valid MAC address,
+	 * set the one from config block if not
+	 */
+	if (!eth_getenv_enetaddr("ethaddr", ethaddr))
+		eth_setenv_enetaddr("ethaddr", (u8 *)&tdx_eth_addr);
+
+#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR
+	if (!eth_getenv_enetaddr("eth1addr", ethaddr)) {
+		/*
+		 * Secondary MAC address is allocated from block
+		 * 0x100000 higher then the first MAC address
+		 */
+		memcpy(ethaddr, &tdx_eth_addr, 6);
+		ethaddr[3] += 0x10;
+		eth_setenv_enetaddr("eth1addr", ethaddr);
+	}
+#endif
+
+	printf("Model: Toradex %s %s, Serial# %s\n",
+	       toradex_modules[tdx_hw_tag.prodid],
+	       tdx_board_rev_str,
+	       tdx_serial_str);
+
+	return 0;
+}
+
+#ifdef CONFIG_USBDOWNLOAD_GADGET
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + tdx_hw_tag.prodid;
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
+#endif /* CONFIG_USBDOWNLOAD_GADGET */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	if (tdx_serial) {
+		fdt_setprop(blob, 0, "serial-number", tdx_serial_str,
+			    strlen(tdx_serial_str) + 1);
+	}
+
+	if (tdx_hw_tag.ver_major) {
+		char prod_id[5];
+
+		sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
+		fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
+
+		fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
+			    strlen(tdx_board_rev_str) + 1);
+	}
+
+	return 0;
+}
+#endif
+
+#else /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+u32 get_board_serial(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+#endif /* CONFIG_TDX_CFG_BLOCK */
diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h
new file mode 100644
index 0000000..f308ebd
--- /dev/null
+++ b/board/toradex/common/tdx-common.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TDX_COMMON_H
+#define _TDX_COMMON_H
+
+#define TORADEX_USB_PRODUCT_NUM_OFFSET	0x4000
+#define TDX_USB_VID			0x1B67
+
+#endif /* _TDX_COMMON_H */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 183f642..2c86940 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static xilinx_desc fpga;
 
 /* It can be done differently */
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
@@ -37,9 +40,18 @@ int board_init(void)
 	idcode = zynq_slcr_get_idcode();
 
 	switch (idcode) {
+	case XILINX_ZYNQ_7007S:
+		fpga = fpga007s;
+		break;
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7012S:
+		fpga = fpga012s;
+		break;
+	case XILINX_ZYNQ_7014S:
+		fpga = fpga014s;
+		break;
 	case XILINX_ZYNQ_7015:
 		fpga = fpga015;
 		break;
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 90f00c6..efc8eda 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -27,3 +27,6 @@ CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
 
 # To include xil_io.h
 CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
+
+# To suppress "warning: cast to pointer from integer of different size"
+CFLAGS_psu_init_gpl.o += -Wno-int-to-pointer-cast
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index 57ca4ad..6bbc000 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -7,6 +7,7 @@
 
 /* FIXME remove this when vivado is fixed */
 #include <asm/io.h>
+#include <common.h>
 
 #define xil_printf(...)
 
@@ -32,4 +33,12 @@ int Xil_In32(unsigned long addr)
 	return readl(addr);
 }
 
+void mask_delay(u32 delay);
+void usleep(u32 sleep)
+{
+	udelay(sleep);
+}
+int mask_poll(u32 add, u32 mask);
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+
 #endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ba4dfbb..cef1f6a 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -86,6 +86,17 @@ static int chip_id(void)
 
 	smc_call(&regs);
 
+	/*
+	 * SMC returns:
+	 * regs[0][31:0]  = status of the operation
+	 * regs[0][63:32] = CSU.IDCODE register
+	 * regs[1][31:0]  = CSU.version register
+	 */
+	regs.regs[0] = upper_32_bits(regs.regs[0]);
+	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+			ZYNQMP_CSU_IDCODE_SVD_MASK;
+	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+
 	return regs.regs[0];
 }
 
@@ -324,6 +335,9 @@ int board_late_init(void)
 	}
 
 	reg = readl(&crlapb_base->boot_mode);
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
 	bootmode = reg & BOOT_MODES_MASK;
 
 	puts("Bootmode: ");
@@ -349,6 +363,9 @@ int board_late_init(void)
 		puts("SD_MODE\n");
 		mode = "mmc0";
 		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
 	case SD_MODE1:
 		puts("SD_MODE1\n");
 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
@@ -411,6 +428,10 @@ int board_usb_init(int index, enum usb_init_type init)
 {
 	debug("%s: index %x\n", __func__, index);
 
+#if defined(CONFIG_USB_GADGET_DOWNLOAD)
+	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
+#endif
+
 	switch (index) {
 	case 0:
 		return dwc3_uboot_init(&dwc3_device_data0);