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| author | Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> | 2014-10-17 18:01:16 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 15:27:29 (GMT) |
| commit | 69a3b811411d7f7d58c1ad587412451e7d4ed412 (patch) | |
| tree | af057747679dbe4a6d48aa97865b8626133f20d2 /board | |
| parent | c05d05e7202b01a1b461c78ba6c5b06545621620 (diff) | |
| download | u-boot-69a3b811411d7f7d58c1ad587412451e7d4ed412.tar.xz | |
ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/ks2_evm/board.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 279ec8e..8991786 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -77,6 +77,7 @@ int board_eth_init(bd_t *bis) return -1; if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; + pass_pll_pa_clk_enable(); port_num = get_num_eth_ports(); |