diff options
author | Tom Rini <trini@konsulko.com> | 2017-06-27 13:32:37 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2017-06-27 13:32:37 (GMT) |
commit | 821560fd8e43eecc208c1c52ad24faadb6b52703 (patch) | |
tree | efb56bc170674d3a6680ca4d343888e9e84403c7 /board | |
parent | b8a238f1376f16c387765107b9d7f62e4358dd48 (diff) | |
parent | 65496a34835cb4c9547bd02dd15b018c333add9d (diff) | |
download | u-boot-821560fd8e43eecc208c1c52ad24faadb6b52703.tar.xz |
Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
include/configs/imx6qdl_icore_rqs.h
include/configs/imx6ul_geam.h
include/configs/imx6ul_isiot.h
Diffstat (limited to 'board')
-rw-r--r-- | board/engicam/common/board.c | 5 | ||||
-rw-r--r-- | board/engicam/geam6ul/Kconfig | 2 | ||||
-rw-r--r-- | board/engicam/icorem6/Kconfig | 2 | ||||
-rw-r--r-- | board/engicam/icorem6_rqs/Kconfig | 2 | ||||
-rw-r--r-- | board/engicam/isiotmx6ul/Kconfig | 2 | ||||
-rw-r--r-- | board/freescale/mx25pdk/mx25pdk.c | 6 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/MAINTAINERS | 4 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/README | 84 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/Kconfig | 15 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/MAINTAINERS | 7 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/Makefile | 6 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/README | 49 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/imximage.cfg | 98 | ||||
-rw-r--r-- | board/technexion/pico-imx7d/pico-imx7d.c | 289 |
14 files changed, 508 insertions, 63 deletions
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index af4ef28..e3bb569 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -53,6 +53,11 @@ int board_late_init(void) break; } + if (is_mx6ul()) + setenv("console", "ttymxc0"); + else + setenv("console", "ttymxc3"); + setenv_fdt_file(); return 0; diff --git a/board/engicam/geam6ul/Kconfig b/board/engicam/geam6ul/Kconfig index 8753d15..7f4023e 100644 --- a/board/engicam/geam6ul/Kconfig +++ b/board/engicam/geam6ul/Kconfig @@ -7,6 +7,6 @@ config SYS_VENDOR default "engicam" config SYS_CONFIG_NAME - default "imx6ul_geam" + default "imx6-engicam" endif diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig index 6d62f0e..4a1c9ac 100644 --- a/board/engicam/icorem6/Kconfig +++ b/board/engicam/icorem6/Kconfig @@ -7,6 +7,6 @@ config SYS_VENDOR default "engicam" config SYS_CONFIG_NAME - default "imx6qdl_icore" + default "imx6-engicam" endif diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig index 1352c68..6dc3a07 100644 --- a/board/engicam/icorem6_rqs/Kconfig +++ b/board/engicam/icorem6_rqs/Kconfig @@ -7,6 +7,6 @@ config SYS_VENDOR default "engicam" config SYS_CONFIG_NAME - default "imx6qdl_icore_rqs" + default "imx6-engicam" endif diff --git a/board/engicam/isiotmx6ul/Kconfig b/board/engicam/isiotmx6ul/Kconfig index 213ffad..10c2c50 100644 --- a/board/engicam/isiotmx6ul/Kconfig +++ b/board/engicam/isiotmx6ul/Kconfig @@ -7,6 +7,6 @@ config SYS_VENDOR default "engicam" config SYS_CONFIG_NAME - default "imx6ul_isiot" + default "imx6-engicam" endif diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 788d3c3..cab769c 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); + /* + * Set the eSDHC1 PER clock to the maximum frequency lower than or equal + * to 50 MHz that can be obtained, which requires to use UPLL as the + * clock source. This actually gives 48 MHz. + */ + imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000); esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS index add2314..9575261 100644 --- a/board/freescale/mx6sabresd/MAINTAINERS +++ b/board/freescale/mx6sabresd/MAINTAINERS @@ -3,6 +3,4 @@ M: Fabio Estevam <fabio.estevam@nxp.com> S: Maintained F: board/freescale/mx6sabresd/ F: include/configs/mx6sabresd.h -F: configs/mx6dlsabresd_defconfig -F: configs/mx6qsabresd_defconfig -F: configs/mx6sabresd_spl_defconfig +F: configs/mx6sabresd_defconfig diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README index bc0c0d0..4b4df06 100644 --- a/board/freescale/mx6sabresd/README +++ b/board/freescale/mx6sabresd/README @@ -1,56 +1,47 @@ -How to use and build U-Boot on mx6sabresd: ----------------------------------- - -Currently there are four methods for booting mx6sabresd boards: +How to use and build U-Boot on mx6sabresd +----------------------------------------- -1. Booting from SD card via normal U-Boot (u-boot.imx) +The following methods can be used for booting mx6sabresd boards: -2. Booting from eMMC via normal U-Boot +1. Booting from SD card -3. Booting via SPL (SPL and u-boot.img) +2. Booting from eMMC -4. Booting via Falcon mode (SPL launches the kernel directly) +3. Booting via Falcon mode (SPL launches the kernel directly) -1. Booting from SD card via normal U-Boot ------------------------------------------ +1. Booting from SD card via SPL +------------------------------- -$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) +mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants. -or +In order to build it: -$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd) +$ make mx6sabresd_defconfig $ make -This will generate the image called u-boot.imx. +This will generate the SPL and u-boot.img binaries. -- Flash the u-boot.imx binary into the SD card: +- Flash the SPL binary into the SD card: -$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync +$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync +- Flash the u-boot.img binary into the SD card: -2. Booting from eMMC via normal U-Boot --------------------------------------- +$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync -$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) -or +2. Booting from eMMC +-------------------- -$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd) +$ make mx6sabresd_defconfig $ make -This will generate the image called u-boot.imx. - -- Flash the u-boot.imx binary into the eMMC: - -Set SW6 to download mode: 00001100 +This will generate the SPL and u-boot.img binaries. -Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader -tool (https://github.com/boundarydevices/imx_usb_loader): - -$ sudo ./imx_usb u-boot.imx +- Boot first from SD card as shown in the previous section In U-boot change the eMMC partition config: @@ -60,48 +51,29 @@ Mount the eMMC in the host PC: => ums 0 mmc 2 -Flash the u-boot.imx binary +- Flash SPL and u-boot.img binaries into the eMMC: -$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync +$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync +$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync Set SW6 to eMMC 8-bit boot: 11010110 -3. Booting via SPL ------------------- - -Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is -through SPL. In order to do so: - -$ make mx6sabresd_spl_defconfig -$ make - -This will generate the SPL image called SPL and the u-boot.img. - -- Flash the SPL image into the SD card: - -$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync - -- Flash the u-boot.img image into the SD card: - -$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync - - -4. Booting via Falcon mode +3. Booting via Falcon mode -------------------------- -$ make mx6sabresd_spl_defconfig +$ make mx6sabresd_defconfig $ make This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the SD card: -$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 oflag=sync status=none && sync +$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync - Flash the u-boot.img image into the SD card: -$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 oflag=sync status=none && sync +$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync Create a partition for root file system and extract it there: diff --git a/board/technexion/pico-imx7d/Kconfig b/board/technexion/pico-imx7d/Kconfig new file mode 100644 index 0000000..f4ae18c --- /dev/null +++ b/board/technexion/pico-imx7d/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PICO_IMX7D + +config SYS_BOARD + default "pico-imx7d" + +config SYS_VENDOR + default "technexion" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "pico-imx7d" + +endif diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS new file mode 100644 index 0000000..276162a --- /dev/null +++ b/board/technexion/pico-imx7d/MAINTAINERS @@ -0,0 +1,7 @@ +Technexion PICO-IMX7D board +M: Wig Cheng <wig.cheng@technexion.com> +M: Vanessa Maegima <vanessa.maegima@nxp.com> +S: Maintained +F: board/technexion/pico-imx7d/ +F: include/configs/pico-imx7d.h +F: configs/pico-imx7d_defconfig diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile new file mode 100644 index 0000000..42cca47 --- /dev/null +++ b/board/technexion/pico-imx7d/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2017 NXP Semiconductors +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pico-imx7d.o diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README new file mode 100644 index 0000000..a2805ee --- /dev/null +++ b/board/technexion/pico-imx7d/README @@ -0,0 +1,49 @@ +How to update U-Boot on pico-imx7d board +---------------------------------------- + +Required software on the host PC: + +- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader + +Build U-Boot for pico: + +$ make mrproper +$ make pico-imx7d_defconfig +$ make + +This generates the U-Boot binary called u-boot.imx. + +Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide +page 3) + +Connect a USB to serial adapter between the host PC and pico. + +Connect a USB cable between the OTG pico port and the host PC. + +Open a terminal program such as minicom. + +Copy u-boot.imx to the imx_usb_loader folder. + +Load u-boot.imx via USB: + +$ sudo ./imx_usb u-boot.imx + +Then U-Boot starts and its messages appear in the console program. + +Use the default environment variables: + +=> env default -f -a +=> saveenv + +Run the UMS command: +=> ums 0 mmc 0 + +Transfer u-boot.imx to be flashed into the eMMC: + +$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync + +Remove power from the pico board. + +Put pico board into normal boot mode. + +Power up the board and the new updated U-Boot should boot from eMMC. diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg new file mode 100644 index 0000000..202956a --- /dev/null +++ b/board/technexion/pico-imx7d/imximage.cfg @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +/* Secure boot support */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c new file mode 100644 index 0000000..799751d --- /dev/null +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2017 NXP Semiconductors + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <miiphy.h> +#include <mmc.h> +#include <netdev.h> +#include <usb.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../../freescale/common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C4 for PMIC */ +static struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, + .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, + .gp = IMX_GPIO_NR(6, 16), + }, + .sda = { + .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, + .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, + .gp = IMX_GPIO_NR(6, 17), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 3 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 1.025V */ + reg = 0xd; + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + + /* decrease SW1B normal voltage to 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(975); + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11) + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + gpio_direction_output(FEC1_RST_GPIO, 0); + udelay(500); + gpio_set_value(FEC1_RST_GPIO, 1); +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(); + + return fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + return set_clk_enet(ENET_125MHz); +} + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe7; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Assume uSDHC3 emmc is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + return 0; +} + +int checkboard(void) +{ + puts("Board: i.MX7D PICOSOM\n"); + + return 0; +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_DEVICE; +} |