ti816x: Rework DDR initialization sequence

The ti816x/am389x SoC is the first generation in what U-Boot calls the
"am33xx" family.  In the first generation of this family the DDR
initialization sequence is quite different from all of the subsequent
generations.  Whereas with ti814x (second generation) we can easily work
the minor differenced between that and am33xx (third generation), our
attempts to do this for ti816x weren't sufficient.  Rather than add a
large amount of #ifdef logic to make this different sequence work we add
a new file, ti816x_emif4.c to handle the various required undocumented
register writes and sequence and leverage what we can from
arch/arm/mach-omap2/am33xx/ddr.c still.  As DDR2 has similar problems
today but I am unable to test it, we drop the DDR2 defines from the code
rather than imply that it works by leaving it.  We also remove a bunch
of other untested code about changing the speed the DDR runs at.

Signed-off-by: Tom Rini <trini@konsulko.com>

1 files changed, 42 insertions, 150 deletions

diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index b6bf162..ad98e09 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -41,176 +41,68 @@ static struct module_pin_mux mmc_pin_mux[] = {
 	{ -1 },
 };
 
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
-	.dmm_lisa_map_0 = 0x00000000,
-	.dmm_lisa_map_1 = 0x00000000,
-	.dmm_lisa_map_2 = 0x80640300,
-	.dmm_lisa_map_3 = 0xC0640320,
-};
-
-/*
- * DDR2 related definitions
- */
-#ifdef CONFIG_TI816X_EVM_DDR2
-static struct ddr_data ddr2_data = {
-	.datardsratio0		= ((0x40<<10) | (0x40<<0)),
-	.datawdsratio0		= ((0x4A<<10) | (0x4A<<0)),
-	.datawiratio0		= ((0x0<<10) | (0x0<<0)),
-	.datagiratio0		= ((0x0<<10) | (0x0<<0)),
-	.datafwsratio0		= ((0x13A<<10) | (0x13A<<0)),
-	.datawrsratio0		= ((0x8A<<10) | (0x8A<<0)),
-};
-
-static struct cmd_control ddr2_ctrl = {
-	.cmd0csratio	= 0x80,
-	.cmd0iclkout	= 0x00,
-
-	.cmd1csratio	= 0x80,
-	.cmd1iclkout	= 0x00,
-
-	.cmd2csratio	= 0x80,
-	.cmd2iclkout	= 0x00,
-
-};
-
-static struct emif_regs ddr2_emif0_regs = {
-	.sdram_config		= 0x43801A3A,
-	.ref_ctrl		= 0x10000C30,
-	.sdram_tim1		= 0x0AAB15E2,
-	.sdram_tim2		= 0x423631D2,
-	.sdram_tim3		= 0x0080032F,
-	.emif_ddr_phy_ctlr_1	= 0x0, /* depend on cpu rev, set later */
-};
+void set_uart_mux_conf(void) {}
 
-static struct emif_regs ddr2_emif1_regs = {
-	.sdram_config		= 0x43801A3A,
-	.ref_ctrl		= 0x10000C30,
-	.sdram_tim1		= 0x0AAB15E2,
-	.sdram_tim2		= 0x423631D2,
-	.sdram_tim3		= 0x0080032F,
-	.emif_ddr_phy_ctlr_1	= 0x0, /* depend on cpu rev, set later */
-};
-#endif
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(mmc_pin_mux);
+}
 
 /*
- * DDR3 related definitions
+ * EMIF Paramters.  Refer the EMIF register documentation and the
+ * memory datasheet for details.  This is for 796 MHz.
  */
-
-#if defined(CONFIG_TI816X_DDR_PLL_400)
-#define RD_DQS		0x03B
-#define WR_DQS		0x0A6
-#define RD_DQS_GATE	0x12A
-#define EMIF_SDCFG	0x62A41032
-#define EMIF_SDREF	0x10000C30
-#define EMIF_TIM1	0x0CCCE524
-#define EMIF_TIM2	0x30308023
-#define EMIF_TIM3	0x009F82CF
-#define EMIF_PHYCFG	0x0000010B
-#elif defined(CONFIG_TI816X_DDR_PLL_531)
-#define RD_DQS		0x039
-#define WR_DQS		0x0B4
-#define RD_DQS_GATE	0x13D
-#define EMIF_SDCFG	0x62A51832
-#define EMIF_SDREF	0x1000102E
-#define EMIF_TIM1	0x0EF136AC
-#define EMIF_TIM2	0x30408063
-#define EMIF_TIM3	0x009F83AF
-#define EMIF_PHYCFG	0x0000010C
-#elif defined(CONFIG_TI816X_DDR_PLL_675)
-#define RD_DQS		0x039
-#define WR_DQS		0x091
-#define RD_DQS_GATE	0x196
-#define EMIF_SDCFG	0x62A63032
-#define EMIF_SDREF	0x10001491
-#define EMIF_TIM1	0x13358875
-#define EMIF_TIM2	0x5051806C
-#define EMIF_TIM3	0x009F84AF
-#define EMIF_PHYCFG	0x0000010F
-#elif defined(CONFIG_TI816X_DDR_PLL_796)
-#define RD_DQS		0x035
-#define WR_DQS		0x093
-#define RD_DQS_GATE	0x1B3
-#define EMIF_SDCFG	0x62A73832
-#define EMIF_SDREF	0x10001841
-#define EMIF_TIM1	0x1779C9FE
-#define EMIF_TIM2	0x50608074
-#define EMIF_TIM3	0x009F857F
-#define EMIF_PHYCFG	0x00000110
-#endif
-
-static struct ddr_data ddr3_data = {
-	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
-	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
-	.datawiratio0		= ((0x20<<10) | 0x20<<0),
-	.datagiratio0		= ((0x20<<10) | 0x20<<0),
-	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
-	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+#define EMIF_TIM1   0x1779C9FE
+#define EMIF_TIM2   0x50608074
+#define EMIF_TIM3   0x009F857F
+#define EMIF_SDREF  0x10001841
+#define EMIF_SDCFG  0x62A73832
+#define EMIF_PHYCFG 0x00000110
+static const struct emif_regs ddr3_emif_regs = {
+	.sdram_config		= EMIF_SDCFG,
+	.ref_ctrl		= EMIF_SDREF,
+	.sdram_tim1		= EMIF_TIM1,
+	.sdram_tim2		= EMIF_TIM2,
+	.sdram_tim3		= EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
 };
 
 static const struct cmd_control ddr3_ctrl = {
 	.cmd0csratio	= 0x100,
 	.cmd0iclkout	= 0x001,
-
 	.cmd1csratio	= 0x100,
 	.cmd1iclkout	= 0x001,
-
 	.cmd2csratio	= 0x100,
 	.cmd2iclkout	= 0x001,
 };
 
-static const struct emif_regs ddr3_emif0_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE	(0x1B3)
+#define RD_DQS		(0x35)
+#define WR_DQS		(0x93)
+static struct ddr_data ddr3_data = {
+	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
+	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
+	.datawiratio0		= ((0x20<<10) | 0x20<<0),
+	.datagiratio0		= ((0x20<<10) | 0x20<<0),
+	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 };
 
-static const struct emif_regs ddr3_emif1_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
+static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+	.dmm_lisa_map_0 = 0x00000000,
+	.dmm_lisa_map_1 = 0x00000000,
+	.dmm_lisa_map_2 = 0x80640300,
+	.dmm_lisa_map_3 = 0xC0640320,
 };
 
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
-	configure_module_pin_mux(mmc_pin_mux);
-}
-
 void sdram_init(void)
 {
-	config_dmm(&evm_lisa_map_regs);
-
-#ifdef CONFIG_TI816X_EVM_DDR2
-	if (CONFIG_TI816X_USE_EMIF0) {
-		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
-			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
-			   0);
-	}
-
-	if (CONFIG_TI816X_USE_EMIF1) {
-		ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
-			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
-			   1);
-	}
-#endif
-
-#ifdef CONFIG_TI816X_EVM_DDR3
-	if (CONFIG_TI816X_USE_EMIF0)
-		config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
-			   0);
-
-	if (CONFIG_TI816X_USE_EMIF1)
-		config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
-			   1);
-#endif
+	/*
+	 * Pass in our DDR3 config information and that we have 2 EMIFs to
+	 * configure.
+	 */
+	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
+			&evm_lisa_map_regs, 2);
 }
 #endif /* CONFIG_SPL_BUILD */