diff options
author | Andy Fleming <afleming@freescale.com> | 2007-08-14 05:14:25 (GMT) |
---|---|---|
committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 06:47:44 (GMT) |
commit | da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 (patch) | |
tree | 878ce01e8e6059383e74d42fdc809b8087a1fcdd /board | |
parent | c59e4091ffe0148398b9e9ff14a019ea038b7432 (diff) | |
download | u-boot-da9d4610d76e52c4d20a8f3d8433439a7fcf5b71.tar.xz |
Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/mpc8568mds/bcsr.c | 7 | ||||
-rw-r--r-- | board/mpc8568mds/bcsr.h | 1 | ||||
-rw-r--r-- | board/mpc8568mds/mpc8568mds.c | 61 |
3 files changed, 68 insertions, 1 deletions
diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd..aae0f98 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f..aefd9bf 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec..818ff13 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include <asm/immap_85xx.h> #include <spd.h> #include <i2c.h> +#include <ioports.h> #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } |