diff options
| author | Nishanth Menon <nm@ti.com> | 2016-04-21 19:34:25 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-25 19:10:41 (GMT) |
| commit | e52e334e5cb493e19377d23a00aa4d021fc229ba (patch) | |
| tree | 87c17eb14060b64ac0dc46ec376ce46439d9a678 /board | |
| parent | a818097a330e73795dc0e783fbb67c5ec86b657f (diff) | |
| download | u-boot-e52e334e5cb493e19377d23a00aa4d021fc229ba.tar.xz | |
ARM: DRA7: Add ABB setup for all domains
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/am57xx/board.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2404eb5..86b8f6e 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -228,12 +228,14 @@ struct vcores_data beagle_x15_volts = { .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, .core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, @@ -246,6 +248,7 @@ struct vcores_data beagle_x15_volts = { .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; #ifdef CONFIG_SPL_BUILD |