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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2017-04-25 18:44:33 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-05-18 09:33:16 (GMT) |
| commit | de7781158923a9c87debc5a89ce4fabfd0fc93bc (patch) | |
| tree | 2f688d87f0559d5c19d48f633681abffd10d5f52 /cmd | |
| parent | fa8967cfbaed5582ba987756fa9f0470a9affbf4 (diff) | |
| download | u-boot-de7781158923a9c87debc5a89ce4fabfd0fc93bc.tar.xz | |
arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'cmd')
0 files changed, 0 insertions, 0 deletions