diff options
| author | Heiko Stübner <heiko@sntech.de> | 2017-03-26 19:09:55 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-04-05 02:01:57 (GMT) |
| commit | 47197682ef8288a610ad22eeac9ec92689a9648d (patch) | |
| tree | 636b98155eb33f5dfbd6f1b0bf01227695554151 /configs/rock_defconfig | |
| parent | ab4458bdb5074ababe09f2538cb9f25901121ebb (diff) | |
| download | u-boot-47197682ef8288a610ad22eeac9ec92689a9648d.tar.xz | |
rockchip: rk3188: Add Radxa Rock board
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/rock_defconfig')
| -rw-r--r-- | configs/rock_defconfig | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/configs/rock_defconfig b/configs/rock_defconfig new file mode 100644 index 0000000..20a065a --- /dev/null +++ b/configs/rock_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3188=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_ROCK=y +CONFIG_SPL_STACK_R_ADDR=0x60080000 +CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_RK3188_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_ACT8846=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x20064000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y |