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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-05 11:06:31 (GMT) |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-05 11:06:31 (GMT) |
commit | b3acb6cd4059dfb29a5e99095d802717f53ff784 (patch) | |
tree | 0578103fde893d08e5b6127db4df18833ae3d075 /cpu/arm1136 | |
parent | 677e62f43235de9a1701204d7bcea0fb3d233fa1 (diff) | |
download | u-boot-b3acb6cd4059dfb29a5e99095d802717f53ff784.tar.xz |
arm: clean cache management
unify arm cache management except for non standard cache as ARM7TDMI
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm1136')
-rw-r--r-- | cpu/arm1136/cpu.c | 46 |
1 files changed, 10 insertions, 36 deletions
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 0abe307..78f6e92 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -39,13 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void); int cpu_init (void) { @@ -68,8 +62,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); #ifdef CONFIG_LCD @@ -83,15 +75,12 @@ int cleanup_before_linux (void) #endif /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ - return(0); + cache_flush(); + + return 0; } int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -102,25 +91,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return(0); } -void icache_enable (void) +static void cache_flush(void) { - ulong reg; + unsigned long i = 0; - reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return(get_cr () & CR_I) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ } |