diff options
author | Jens Scharsig <js_at_ng@scharsoft.de> | 2010-02-03 21:46:58 (GMT) |
---|---|---|
committer | Tom Rix <Tom.Rix@windriver.com> | 2010-02-12 18:31:55 (GMT) |
commit | 0cf0b93161beb3f3ed5e37e6112aedf15da17e8a (patch) | |
tree | b620b5a93d12d5039bc541be298165a7f06f2212 /cpu/arm926ejs | |
parent | 7f9e8633ac9c846e7e4f867507cbd5de1bd99e0c (diff) | |
download | u-boot-0cf0b93161beb3f3ed5e37e6112aedf15da17e8a.tar.xz |
convert common files to new SoC access
* add's a warning to all files, which need update to new SoC access
* convert common files in cpu/../at91 and a lot of drivers to use
c stucture SoC access
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Diffstat (limited to 'cpu/arm926ejs')
-rw-r--r-- | cpu/arm926ejs/at91/at91cap9_devices.c | 28 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/at91sam9260_devices.c | 24 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/at91sam9261_devices.c | 24 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/at91sam9263_devices.c | 33 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 24 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/at91sam9rl_devices.c | 20 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/clock.c | 51 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/cpu.c | 4 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/led.c | 1 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/lowlevel_init.S | 95 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/reset.c | 8 | ||||
-rw-r--r-- | cpu/arm926ejs/at91/timer.c | 17 |
12 files changed, 208 insertions, 121 deletions
diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 518a8d7..2d878fd 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -34,30 +34,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); + writel(1 << AT91CAP9_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); + writel(1 << AT91CAP9_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); + writel(1 << AT91CAP9_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -82,12 +90,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); + writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -117,12 +127,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1); + writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -182,10 +194,12 @@ void at91_macb_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN); + writel(1 << AT91CAP9_ID_CAN, &pmc->pcer); } #endif diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 68c1974..77d49ab 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + writel(1 << AT91SAM9260_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + writel(1 << AT91SAM9260_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + writel(1 << AT91SAM9260_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); + writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1); + writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 286e72a..b4353ef 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); + writel(1 << AT91SAM9261_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); + writel(1 << AT91SAM9261_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); + writel(1 << AT91SAM9261_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); + writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); + writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index 90bdcc2..deda3e5 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -27,37 +27,46 @@ */ #include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); + writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); + writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -82,12 +91,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); + writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -117,12 +128,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); + writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -190,10 +203,12 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); + writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); } #endif diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 6881e46..4ad9b1f 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); + writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); + writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); + writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); + writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 0); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1); + writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 0); diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index d74e144..4f570f4 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); + writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); + writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); + writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); + writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 574f488..7e03907 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -13,9 +13,9 @@ #include <config.h> #include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> static unsigned long cpu_clk_rate_hz; static unsigned long main_clk_rate_hz; @@ -57,14 +57,14 @@ u32 get_pllb_init(void) static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { - case AT91_PMC_CSS_SLOW: - return AT91_SLOW_CLOCK; - case AT91_PMC_CSS_MAIN: - return main_clk_rate_hz; - case AT91_PMC_CSS_PLLA: - return plla_rate_hz; - case AT91_PMC_CSS_PLLB: - return pllb_rate_hz; + case AT91_PMC_MCKR_CSS_SLOW: + return AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return pllb_rate_hz; } return 0; @@ -146,6 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; #ifndef AT91_MAIN_CLOCK unsigned tmp; /* @@ -164,7 +165,7 @@ int at91_clock_init(unsigned long main_clock) main_clk_rate_hz = main_clock; /* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); #ifdef CONFIG_USB_ATMEL /* @@ -174,7 +175,7 @@ int at91_clock_init(unsigned long main_clock) * REVISIT: assumes MCK doesn't derive from PLLB! */ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_USB96M; + AT91_PMC_PLLBR_USBDIV_2; pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); #endif @@ -182,28 +183,32 @@ int at91_clock_init(unsigned long main_clock) * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = readl(&pmc->mckr); #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* plla divisor by 2 */ plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif - freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = mck_rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* mdiv */ + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #elif defined(CONFIG_AT91SAM9G20) - mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? - freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #endif cpu_clk_rate_hz = freq; - return 0; + return 0; } diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..993b299 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -22,6 +22,10 @@ */ #include <common.h> +#ifdef CONFIG_AT91_LEGACY +#warning Your board is using legacy SoC access. Please update! +#endif + #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c index be68f59..0a315c4 100644 --- a/cpu/arm926ejs/at91/led.c +++ b/cpu/arm926ejs/at91/led.c @@ -24,6 +24,7 @@ #include <common.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index f11ebc6..559c35c 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -27,15 +27,20 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_wdt.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_matrix.h> #include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_rstc.h> +#ifdef CONFIG_AT91_LEGACY +#include <asm/arch/at91sam9_matrix.h> +#endif +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#endif _TEXT_BASE: .word TEXT_BASE @@ -75,7 +80,7 @@ POS1: * - Check if the PLL is already initialized * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) ldr r0, [r1] and r0, r0, #3 cmp r0, #0 @@ -85,18 +90,18 @@ POS1: * - Enable the Main Oscillator * --------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r1, =(AT91_ASM_PMC_MOR) + ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS + mov r4, #AT91_PMC_IXR_MOSCS MOSCS_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS + cmp r3, #AT91_PMC_IXR_MOSCS bne MOSCS_Loop /* ---------------------------------------------------------------------------- @@ -105,16 +110,16 @@ MOSCS_Loop: * Setup PLLA * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r1, =(AT91_ASM_PMC_PLLAR) ldr r0, =CONFIG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA + mov r4, #AT91_PMC_IXR_LOCKA MOSCS_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA + cmp r3, #AT91_PMC_IXR_LOCKA bne MOSCS_Loop1 /* ---------------------------------------------------------------------------- @@ -123,38 +128,37 @@ MOSCS_Loop1: * - Switch on the Main Oscillator * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ ldr r0, =CONFIG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IXR_MCKRDY MCKRDY_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop ldr r0, =CONFIG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IXR_MCKRDY MCKRDY_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop1 - PLL_setup_end: /* ---------------------------------------------------------------------------- * - memory control configuration 2 * ---------------------------------------------------------------------------- */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + ldr r0, =(AT91_ASM_SDRAMC_TR) ldr r1, [r0] cmp r1, #0 bne SDRAM_setup_end @@ -166,7 +170,6 @@ PLL_setup_end: sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 - 2: /* the address */ ldr r1, [r0], #4 @@ -183,60 +186,53 @@ SDRAM_setup_end: .ltorg SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) + .word AT91_ASM_WDT_MR .word CONFIG_SYS_WDTC_WDMR_VAL - /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word AT91_ASM_PIOD_PDR .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word AT91_ASM_PIOD_PUDR .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word AT91_ASM_PIOD_ASR .word CONFIG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word AT91_ASM_PIOC_PDR .word CONFIG_SYS_PIOC_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word AT91_ASM_PIOC_PUDR .word CONFIG_SYS_PIOC_PPUDR_VAL #endif - -#if defined(AT91_MATRIX_EBI0CSA) - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL -#else /* AT91_MATRIX_EBICSA */ - .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word AT91_ASM_MATRIX_CSA0 .word CONFIG_SYS_MATRIX_EBICSA_VAL -#endif /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word AT91_ASM_SMC_MODE0 .word CONFIG_SYS_SMC0_MODE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word AT91_ASM_SMC_CYCLE0 .word CONFIG_SYS_SMC0_CYCLE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word AT91_ASM_SMC_PULSE0 .word CONFIG_SYS_SMC0_PULSE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word AT91_ASM_SMC_SETUP0 .word CONFIG_SYS_SMC0_SETUP0_VAL SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word AT91_ASM_SDRAMC_CR .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word AT91_ASM_SDRAMC_MDR .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 @@ -254,26 +250,25 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL8 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word AT91_ASM_MATRIX_MCFG .word 0x1FF #endif - SMRDATA2: .word 0 diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c index f963e14..1b67e77 100644 --- a/cpu/arm926ejs/at91/reset.c +++ b/cpu/arm926ejs/at91/reset.c @@ -32,10 +32,12 @@ */ void reset_cpu(ulong ignored) { + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + /* this is the way Linux does it */ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | - AT91_RSTC_PROCRST | - AT91_RSTC_PERRST); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, + &rstc->cr); while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index 7352b5c..d21eebf 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -35,8 +35,6 @@ * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) -#define READ_TIMER at91_sys_read(AT91_PIT_PIIR) static ulong timestamp; static ulong lastinc; @@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) /* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); /* Enable PITC */ - at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); reset_timer_masked(); @@ -82,7 +82,9 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + ulong now = readl(&pit->piir); if (now >= lastinc) /* normal mode (non roll) */ /* move stamp forward with absolut diff ticks */ @@ -96,7 +98,10 @@ unsigned long long get_ticks(void) void reset_timer_masked(void) { /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + /* capture current incrementer value time */ + lastinc = readl(&pit->piir); timestamp = 0; /* start "advancing" time stamp from 0 */ } |